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303 lines
7.5 KiB
303 lines
7.5 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ |
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#ifndef _IONIC_LIF_H_ |
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#define _IONIC_LIF_H_ |
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#include <linux/dim.h> |
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#include <linux/pci.h> |
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#include "ionic_rx_filter.h" |
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#define IONIC_ADMINQ_LENGTH 16 /* must be a power of two */ |
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#define IONIC_NOTIFYQ_LENGTH 64 /* must be a power of two */ |
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#define IONIC_MAX_NUM_NAPI_CNTR (NAPI_POLL_WEIGHT + 1) |
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#define IONIC_MAX_NUM_SG_CNTR (IONIC_TX_MAX_SG_ELEMS + 1) |
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#define ADD_ADDR true |
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#define DEL_ADDR false |
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#define CAN_SLEEP true |
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#define CAN_NOT_SLEEP false |
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#define IONIC_RX_COPYBREAK_DEFAULT 256 |
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#define IONIC_TX_BUDGET_DEFAULT 256 |
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struct ionic_tx_stats { |
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u64 pkts; |
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u64 bytes; |
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u64 csum_none; |
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u64 csum; |
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u64 tso; |
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u64 tso_bytes; |
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u64 frags; |
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u64 vlan_inserted; |
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u64 clean; |
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u64 linearize; |
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u64 crc32_csum; |
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u64 sg_cntr[IONIC_MAX_NUM_SG_CNTR]; |
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u64 dma_map_err; |
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}; |
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struct ionic_rx_stats { |
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u64 pkts; |
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u64 bytes; |
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u64 csum_none; |
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u64 csum_complete; |
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u64 buffers_posted; |
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u64 dropped; |
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u64 vlan_stripped; |
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u64 csum_error; |
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u64 dma_map_err; |
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u64 alloc_err; |
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}; |
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#define IONIC_QCQ_F_INITED BIT(0) |
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#define IONIC_QCQ_F_SG BIT(1) |
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#define IONIC_QCQ_F_INTR BIT(2) |
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#define IONIC_QCQ_F_TX_STATS BIT(3) |
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#define IONIC_QCQ_F_RX_STATS BIT(4) |
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#define IONIC_QCQ_F_NOTIFYQ BIT(5) |
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struct ionic_napi_stats { |
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u64 poll_count; |
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u64 work_done_cntr[IONIC_MAX_NUM_NAPI_CNTR]; |
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}; |
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struct ionic_qcq { |
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void *q_base; |
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dma_addr_t q_base_pa; |
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u32 q_size; |
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void *cq_base; |
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dma_addr_t cq_base_pa; |
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u32 cq_size; |
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void *sg_base; |
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dma_addr_t sg_base_pa; |
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u32 sg_size; |
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struct dim dim; |
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struct ionic_queue q; |
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struct ionic_cq cq; |
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struct ionic_intr_info intr; |
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struct napi_struct napi; |
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struct ionic_napi_stats napi_stats; |
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unsigned int flags; |
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struct dentry *dentry; |
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}; |
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#define q_to_qcq(q) container_of(q, struct ionic_qcq, q) |
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#define q_to_tx_stats(q) (&(q)->lif->txqstats[(q)->index]) |
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#define q_to_rx_stats(q) (&(q)->lif->rxqstats[(q)->index]) |
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#define napi_to_qcq(napi) container_of(napi, struct ionic_qcq, napi) |
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#define napi_to_cq(napi) (&napi_to_qcq(napi)->cq) |
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enum ionic_deferred_work_type { |
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IONIC_DW_TYPE_RX_MODE, |
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IONIC_DW_TYPE_RX_ADDR_ADD, |
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IONIC_DW_TYPE_RX_ADDR_DEL, |
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IONIC_DW_TYPE_LINK_STATUS, |
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IONIC_DW_TYPE_LIF_RESET, |
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}; |
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struct ionic_deferred_work { |
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struct list_head list; |
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enum ionic_deferred_work_type type; |
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union { |
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unsigned int rx_mode; |
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u8 addr[ETH_ALEN]; |
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u8 fw_status; |
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}; |
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}; |
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struct ionic_deferred { |
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spinlock_t lock; /* lock for deferred work list */ |
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struct list_head list; |
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struct work_struct work; |
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}; |
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struct ionic_lif_sw_stats { |
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u64 tx_packets; |
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u64 tx_bytes; |
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u64 rx_packets; |
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u64 rx_bytes; |
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u64 tx_tso; |
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u64 tx_tso_bytes; |
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u64 tx_csum_none; |
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u64 tx_csum; |
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u64 rx_csum_none; |
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u64 rx_csum_complete; |
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u64 rx_csum_error; |
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u64 hw_tx_dropped; |
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u64 hw_rx_dropped; |
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u64 hw_rx_over_errors; |
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u64 hw_rx_missed_errors; |
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u64 hw_tx_aborted_errors; |
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}; |
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enum ionic_lif_state_flags { |
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IONIC_LIF_F_INITED, |
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IONIC_LIF_F_SW_DEBUG_STATS, |
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IONIC_LIF_F_UP, |
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IONIC_LIF_F_LINK_CHECK_REQUESTED, |
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IONIC_LIF_F_FW_RESET, |
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IONIC_LIF_F_SPLIT_INTR, |
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IONIC_LIF_F_TX_DIM_INTR, |
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IONIC_LIF_F_RX_DIM_INTR, |
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/* leave this as last */ |
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IONIC_LIF_F_STATE_SIZE |
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}; |
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struct ionic_qtype_info { |
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u8 version; |
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u8 supported; |
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u64 features; |
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u16 desc_sz; |
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u16 comp_sz; |
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u16 sg_desc_sz; |
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u16 max_sg_elems; |
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u16 sg_desc_stride; |
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}; |
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#define IONIC_LIF_NAME_MAX_SZ 32 |
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struct ionic_lif { |
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char name[IONIC_LIF_NAME_MAX_SZ]; |
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struct list_head list; |
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struct net_device *netdev; |
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DECLARE_BITMAP(state, IONIC_LIF_F_STATE_SIZE); |
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struct ionic *ionic; |
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bool registered; |
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unsigned int index; |
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unsigned int hw_index; |
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unsigned int kern_pid; |
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u64 __iomem *kern_dbpage; |
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struct mutex queue_lock; /* lock for queue structures */ |
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spinlock_t adminq_lock; /* lock for AdminQ operations */ |
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struct ionic_qcq *adminqcq; |
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struct ionic_qcq *notifyqcq; |
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struct ionic_qcq **txqcqs; |
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struct ionic_tx_stats *txqstats; |
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struct ionic_qcq **rxqcqs; |
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struct ionic_rx_stats *rxqstats; |
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u64 last_eid; |
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unsigned int neqs; |
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unsigned int nxqs; |
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unsigned int ntxq_descs; |
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unsigned int nrxq_descs; |
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u32 rx_copybreak; |
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u32 tx_budget; |
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unsigned int rx_mode; |
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u64 hw_features; |
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bool mc_overflow; |
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unsigned int nmcast; |
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bool uc_overflow; |
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u16 lif_type; |
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unsigned int nucast; |
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union ionic_lif_identity *identity; |
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struct ionic_lif_info *info; |
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dma_addr_t info_pa; |
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u32 info_sz; |
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struct ionic_qtype_info qtype_info[IONIC_QTYPE_MAX]; |
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u16 rss_types; |
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u8 rss_hash_key[IONIC_RSS_HASH_KEY_SIZE]; |
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u8 *rss_ind_tbl; |
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dma_addr_t rss_ind_tbl_pa; |
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u32 rss_ind_tbl_sz; |
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struct ionic_rx_filters rx_filters; |
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struct ionic_deferred deferred; |
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unsigned long *dbid_inuse; |
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unsigned int dbid_count; |
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struct dentry *dentry; |
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u32 rx_coalesce_usecs; /* what the user asked for */ |
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u32 rx_coalesce_hw; /* what the hw is using */ |
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u32 tx_coalesce_usecs; /* what the user asked for */ |
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u32 tx_coalesce_hw; /* what the hw is using */ |
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struct work_struct tx_timeout_work; |
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}; |
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struct ionic_queue_params { |
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unsigned int nxqs; |
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unsigned int ntxq_descs; |
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unsigned int nrxq_descs; |
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unsigned int intr_split; |
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}; |
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static inline void ionic_init_queue_params(struct ionic_lif *lif, |
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struct ionic_queue_params *qparam) |
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{ |
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qparam->nxqs = lif->nxqs; |
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qparam->ntxq_descs = lif->ntxq_descs; |
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qparam->nrxq_descs = lif->nrxq_descs; |
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qparam->intr_split = test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); |
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} |
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static inline u32 ionic_coal_usec_to_hw(struct ionic *ionic, u32 usecs) |
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{ |
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u32 mult = le32_to_cpu(ionic->ident.dev.intr_coal_mult); |
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u32 div = le32_to_cpu(ionic->ident.dev.intr_coal_div); |
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/* Div-by-zero should never be an issue, but check anyway */ |
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if (!div || !mult) |
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return 0; |
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/* Round up in case usecs is close to the next hw unit */ |
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usecs += (div / mult) >> 1; |
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/* Convert from usecs to device units */ |
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return (usecs * mult) / div; |
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} |
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void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep); |
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void ionic_get_stats64(struct net_device *netdev, |
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struct rtnl_link_stats64 *ns); |
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void ionic_lif_deferred_enqueue(struct ionic_deferred *def, |
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struct ionic_deferred_work *work); |
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int ionic_lif_alloc(struct ionic *ionic); |
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int ionic_lif_init(struct ionic_lif *lif); |
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void ionic_lif_free(struct ionic_lif *lif); |
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void ionic_lif_deinit(struct ionic_lif *lif); |
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int ionic_lif_register(struct ionic_lif *lif); |
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void ionic_lif_unregister(struct ionic_lif *lif); |
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int ionic_lif_identify(struct ionic *ionic, u8 lif_type, |
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union ionic_lif_identity *lif_ident); |
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int ionic_lif_size(struct ionic *ionic); |
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int ionic_lif_rss_config(struct ionic_lif *lif, u16 types, |
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const u8 *key, const u32 *indir); |
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int ionic_reconfigure_queues(struct ionic_lif *lif, |
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struct ionic_queue_params *qparam); |
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static inline void debug_stats_txq_post(struct ionic_queue *q, bool dbell) |
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{ |
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struct ionic_txq_desc *desc = &q->txq[q->head_idx]; |
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u8 num_sg_elems; |
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q->dbell_count += dbell; |
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num_sg_elems = ((le64_to_cpu(desc->cmd) >> IONIC_TXQ_DESC_NSGE_SHIFT) |
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& IONIC_TXQ_DESC_NSGE_MASK); |
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if (num_sg_elems > (IONIC_MAX_NUM_SG_CNTR - 1)) |
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num_sg_elems = IONIC_MAX_NUM_SG_CNTR - 1; |
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q->lif->txqstats[q->index].sg_cntr[num_sg_elems]++; |
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} |
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static inline void debug_stats_napi_poll(struct ionic_qcq *qcq, |
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unsigned int work_done) |
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{ |
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qcq->napi_stats.poll_count++; |
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if (work_done > (IONIC_MAX_NUM_NAPI_CNTR - 1)) |
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work_done = IONIC_MAX_NUM_NAPI_CNTR - 1; |
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qcq->napi_stats.work_done_cntr[work_done]++; |
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} |
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#define DEBUG_STATS_CQE_CNT(cq) ((cq)->compl_count++) |
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#define DEBUG_STATS_RX_BUFF_CNT(q) ((q)->lif->rxqstats[q->index].buffers_posted++) |
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#define DEBUG_STATS_TXQ_POST(q, dbell) debug_stats_txq_post(q, dbell) |
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#define DEBUG_STATS_NAPI_POLL(qcq, work_done) \ |
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debug_stats_napi_poll(qcq, work_done) |
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#endif /* _IONIC_LIF_H_ */
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