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650 lines
16 KiB
650 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/errno.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/etherdevice.h> |
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#include "ionic.h" |
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#include "ionic_dev.h" |
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#include "ionic_lif.h" |
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static void ionic_watchdog_cb(struct timer_list *t) |
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{ |
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struct ionic *ionic = from_timer(ionic, t, watchdog_timer); |
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int hb; |
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mod_timer(&ionic->watchdog_timer, |
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round_jiffies(jiffies + ionic->watchdog_period)); |
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if (!ionic->lif) |
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return; |
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hb = ionic_heartbeat_check(ionic); |
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if (hb >= 0) |
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ionic_link_status_check_request(ionic->lif, CAN_NOT_SLEEP); |
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} |
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void ionic_init_devinfo(struct ionic *ionic) |
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{ |
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struct ionic_dev *idev = &ionic->idev; |
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idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type); |
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idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev); |
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memcpy_fromio(idev->dev_info.fw_version, |
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idev->dev_info_regs->fw_version, |
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IONIC_DEVINFO_FWVERS_BUFLEN); |
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memcpy_fromio(idev->dev_info.serial_num, |
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idev->dev_info_regs->serial_num, |
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IONIC_DEVINFO_SERIAL_BUFLEN); |
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idev->dev_info.fw_version[IONIC_DEVINFO_FWVERS_BUFLEN] = 0; |
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idev->dev_info.serial_num[IONIC_DEVINFO_SERIAL_BUFLEN] = 0; |
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dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version); |
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} |
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int ionic_dev_setup(struct ionic *ionic) |
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{ |
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struct ionic_dev_bar *bar = ionic->bars; |
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unsigned int num_bars = ionic->num_bars; |
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struct ionic_dev *idev = &ionic->idev; |
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struct device *dev = ionic->dev; |
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u32 sig; |
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/* BAR0: dev_cmd and interrupts */ |
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if (num_bars < 1) { |
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dev_err(dev, "No bars found, aborting\n"); |
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return -EFAULT; |
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} |
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if (bar->len < IONIC_BAR0_SIZE) { |
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dev_err(dev, "Resource bar size %lu too small, aborting\n", |
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bar->len); |
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return -EFAULT; |
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} |
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idev->dev_info_regs = bar->vaddr + IONIC_BAR0_DEV_INFO_REGS_OFFSET; |
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idev->dev_cmd_regs = bar->vaddr + IONIC_BAR0_DEV_CMD_REGS_OFFSET; |
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idev->intr_status = bar->vaddr + IONIC_BAR0_INTR_STATUS_OFFSET; |
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idev->intr_ctrl = bar->vaddr + IONIC_BAR0_INTR_CTRL_OFFSET; |
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sig = ioread32(&idev->dev_info_regs->signature); |
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if (sig != IONIC_DEV_INFO_SIGNATURE) { |
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dev_err(dev, "Incompatible firmware signature %x", sig); |
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return -EFAULT; |
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} |
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ionic_init_devinfo(ionic); |
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/* BAR1: doorbells */ |
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bar++; |
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if (num_bars < 2) { |
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dev_err(dev, "Doorbell bar missing, aborting\n"); |
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return -EFAULT; |
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} |
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idev->last_fw_status = 0xff; |
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timer_setup(&ionic->watchdog_timer, ionic_watchdog_cb, 0); |
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ionic->watchdog_period = IONIC_WATCHDOG_SECS * HZ; |
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mod_timer(&ionic->watchdog_timer, |
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round_jiffies(jiffies + ionic->watchdog_period)); |
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idev->db_pages = bar->vaddr; |
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idev->phy_db_pages = bar->bus_addr; |
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return 0; |
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} |
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/* Devcmd Interface */ |
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int ionic_heartbeat_check(struct ionic *ionic) |
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{ |
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struct ionic_dev *idev = &ionic->idev; |
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unsigned long hb_time; |
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u8 fw_status; |
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u32 hb; |
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/* wait a little more than one second before testing again */ |
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hb_time = jiffies; |
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if (time_before(hb_time, (idev->last_hb_time + ionic->watchdog_period))) |
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return 0; |
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/* firmware is useful only if the running bit is set and |
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* fw_status != 0xff (bad PCI read) |
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*/ |
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fw_status = ioread8(&idev->dev_info_regs->fw_status); |
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if (fw_status != 0xff) |
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fw_status &= IONIC_FW_STS_F_RUNNING; /* use only the run bit */ |
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/* is this a transition? */ |
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if (fw_status != idev->last_fw_status && |
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idev->last_fw_status != 0xff) { |
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struct ionic_lif *lif = ionic->lif; |
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bool trigger = false; |
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if (!fw_status || fw_status == 0xff) { |
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dev_info(ionic->dev, "FW stopped %u\n", fw_status); |
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if (lif && !test_bit(IONIC_LIF_F_FW_RESET, lif->state)) |
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trigger = true; |
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} else { |
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dev_info(ionic->dev, "FW running %u\n", fw_status); |
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if (lif && test_bit(IONIC_LIF_F_FW_RESET, lif->state)) |
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trigger = true; |
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} |
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if (trigger) { |
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struct ionic_deferred_work *work; |
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work = kzalloc(sizeof(*work), GFP_ATOMIC); |
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if (!work) { |
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dev_err(ionic->dev, "LIF reset trigger dropped\n"); |
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} else { |
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work->type = IONIC_DW_TYPE_LIF_RESET; |
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if (fw_status & IONIC_FW_STS_F_RUNNING && |
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fw_status != 0xff) |
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work->fw_status = 1; |
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ionic_lif_deferred_enqueue(&lif->deferred, work); |
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} |
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} |
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} |
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idev->last_fw_status = fw_status; |
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if (!fw_status || fw_status == 0xff) |
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return -ENXIO; |
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/* early FW has no heartbeat, else FW will return non-zero */ |
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hb = ioread32(&idev->dev_info_regs->fw_heartbeat); |
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if (!hb) |
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return 0; |
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/* are we stalled? */ |
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if (hb == idev->last_hb) { |
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/* only complain once for each stall seen */ |
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if (idev->last_hb_time != 1) { |
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dev_info(ionic->dev, "FW heartbeat stalled at %d\n", |
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idev->last_hb); |
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idev->last_hb_time = 1; |
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} |
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return -ENXIO; |
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} |
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if (idev->last_hb_time == 1) |
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dev_info(ionic->dev, "FW heartbeat restored at %d\n", hb); |
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idev->last_hb = hb; |
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idev->last_hb_time = hb_time; |
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return 0; |
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} |
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u8 ionic_dev_cmd_status(struct ionic_dev *idev) |
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{ |
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return ioread8(&idev->dev_cmd_regs->comp.comp.status); |
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} |
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bool ionic_dev_cmd_done(struct ionic_dev *idev) |
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{ |
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return ioread32(&idev->dev_cmd_regs->done) & IONIC_DEV_CMD_DONE; |
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} |
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void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp) |
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{ |
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memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp)); |
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} |
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void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd) |
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{ |
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memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd)); |
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iowrite32(0, &idev->dev_cmd_regs->done); |
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iowrite32(1, &idev->dev_cmd_regs->doorbell); |
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} |
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/* Device commands */ |
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void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver) |
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{ |
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union ionic_dev_cmd cmd = { |
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.identify.opcode = IONIC_CMD_IDENTIFY, |
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.identify.ver = ver, |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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void ionic_dev_cmd_init(struct ionic_dev *idev) |
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{ |
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union ionic_dev_cmd cmd = { |
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.init.opcode = IONIC_CMD_INIT, |
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.init.type = 0, |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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void ionic_dev_cmd_reset(struct ionic_dev *idev) |
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{ |
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union ionic_dev_cmd cmd = { |
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.reset.opcode = IONIC_CMD_RESET, |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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/* Port commands */ |
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void ionic_dev_cmd_port_identify(struct ionic_dev *idev) |
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{ |
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union ionic_dev_cmd cmd = { |
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.port_init.opcode = IONIC_CMD_PORT_IDENTIFY, |
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.port_init.index = 0, |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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void ionic_dev_cmd_port_init(struct ionic_dev *idev) |
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{ |
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union ionic_dev_cmd cmd = { |
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.port_init.opcode = IONIC_CMD_PORT_INIT, |
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.port_init.index = 0, |
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.port_init.info_pa = cpu_to_le64(idev->port_info_pa), |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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void ionic_dev_cmd_port_reset(struct ionic_dev *idev) |
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{ |
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union ionic_dev_cmd cmd = { |
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.port_reset.opcode = IONIC_CMD_PORT_RESET, |
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.port_reset.index = 0, |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state) |
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{ |
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union ionic_dev_cmd cmd = { |
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.port_setattr.opcode = IONIC_CMD_PORT_SETATTR, |
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.port_setattr.index = 0, |
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.port_setattr.attr = IONIC_PORT_ATTR_STATE, |
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.port_setattr.state = state, |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed) |
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{ |
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union ionic_dev_cmd cmd = { |
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.port_setattr.opcode = IONIC_CMD_PORT_SETATTR, |
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.port_setattr.index = 0, |
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.port_setattr.attr = IONIC_PORT_ATTR_SPEED, |
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.port_setattr.speed = cpu_to_le32(speed), |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable) |
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{ |
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union ionic_dev_cmd cmd = { |
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.port_setattr.opcode = IONIC_CMD_PORT_SETATTR, |
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.port_setattr.index = 0, |
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.port_setattr.attr = IONIC_PORT_ATTR_AUTONEG, |
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.port_setattr.an_enable = an_enable, |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type) |
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{ |
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union ionic_dev_cmd cmd = { |
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.port_setattr.opcode = IONIC_CMD_PORT_SETATTR, |
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.port_setattr.index = 0, |
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.port_setattr.attr = IONIC_PORT_ATTR_FEC, |
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.port_setattr.fec_type = fec_type, |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type) |
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{ |
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union ionic_dev_cmd cmd = { |
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.port_setattr.opcode = IONIC_CMD_PORT_SETATTR, |
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.port_setattr.index = 0, |
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.port_setattr.attr = IONIC_PORT_ATTR_PAUSE, |
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.port_setattr.pause_type = pause_type, |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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/* VF commands */ |
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int ionic_set_vf_config(struct ionic *ionic, int vf, u8 attr, u8 *data) |
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{ |
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union ionic_dev_cmd cmd = { |
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.vf_setattr.opcode = IONIC_CMD_VF_SETATTR, |
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.vf_setattr.attr = attr, |
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.vf_setattr.vf_index = cpu_to_le16(vf), |
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}; |
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int err; |
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switch (attr) { |
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case IONIC_VF_ATTR_SPOOFCHK: |
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cmd.vf_setattr.spoofchk = *data; |
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dev_dbg(ionic->dev, "%s: vf %d spoof %d\n", |
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__func__, vf, *data); |
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break; |
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case IONIC_VF_ATTR_TRUST: |
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cmd.vf_setattr.trust = *data; |
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dev_dbg(ionic->dev, "%s: vf %d trust %d\n", |
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__func__, vf, *data); |
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break; |
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case IONIC_VF_ATTR_LINKSTATE: |
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cmd.vf_setattr.linkstate = *data; |
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dev_dbg(ionic->dev, "%s: vf %d linkstate %d\n", |
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__func__, vf, *data); |
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break; |
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case IONIC_VF_ATTR_MAC: |
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ether_addr_copy(cmd.vf_setattr.macaddr, data); |
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dev_dbg(ionic->dev, "%s: vf %d macaddr %pM\n", |
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__func__, vf, data); |
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break; |
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case IONIC_VF_ATTR_VLAN: |
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cmd.vf_setattr.vlanid = cpu_to_le16(*(u16 *)data); |
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dev_dbg(ionic->dev, "%s: vf %d vlan %d\n", |
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__func__, vf, *(u16 *)data); |
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break; |
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case IONIC_VF_ATTR_RATE: |
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cmd.vf_setattr.maxrate = cpu_to_le32(*(u32 *)data); |
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dev_dbg(ionic->dev, "%s: vf %d maxrate %d\n", |
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__func__, vf, *(u32 *)data); |
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break; |
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case IONIC_VF_ATTR_STATSADDR: |
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cmd.vf_setattr.stats_pa = cpu_to_le64(*(u64 *)data); |
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dev_dbg(ionic->dev, "%s: vf %d stats_pa 0x%08llx\n", |
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__func__, vf, *(u64 *)data); |
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break; |
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default: |
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return -EINVAL; |
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} |
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mutex_lock(&ionic->dev_cmd_lock); |
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ionic_dev_cmd_go(&ionic->idev, &cmd); |
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err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); |
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mutex_unlock(&ionic->dev_cmd_lock); |
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return err; |
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} |
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/* LIF commands */ |
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void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, |
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u16 lif_type, u8 qtype, u8 qver) |
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{ |
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union ionic_dev_cmd cmd = { |
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.q_identify.opcode = IONIC_CMD_Q_IDENTIFY, |
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.q_identify.lif_type = cpu_to_le16(lif_type), |
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.q_identify.type = qtype, |
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.q_identify.ver = qver, |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver) |
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{ |
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union ionic_dev_cmd cmd = { |
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.lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY, |
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.lif_identify.type = type, |
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.lif_identify.ver = ver, |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index, |
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dma_addr_t info_pa) |
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{ |
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union ionic_dev_cmd cmd = { |
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.lif_init.opcode = IONIC_CMD_LIF_INIT, |
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.lif_init.index = cpu_to_le16(lif_index), |
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.lif_init.info_pa = cpu_to_le64(info_pa), |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index) |
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{ |
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union ionic_dev_cmd cmd = { |
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.lif_init.opcode = IONIC_CMD_LIF_RESET, |
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.lif_init.index = cpu_to_le16(lif_index), |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, |
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u16 lif_index, u16 intr_index) |
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{ |
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struct ionic_queue *q = &qcq->q; |
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struct ionic_cq *cq = &qcq->cq; |
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union ionic_dev_cmd cmd = { |
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.q_init.opcode = IONIC_CMD_Q_INIT, |
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.q_init.lif_index = cpu_to_le16(lif_index), |
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.q_init.type = q->type, |
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.q_init.ver = qcq->q.lif->qtype_info[q->type].version, |
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.q_init.index = cpu_to_le32(q->index), |
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.q_init.flags = cpu_to_le16(IONIC_QINIT_F_IRQ | |
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IONIC_QINIT_F_ENA), |
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.q_init.pid = cpu_to_le16(q->pid), |
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.q_init.intr_index = cpu_to_le16(intr_index), |
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.q_init.ring_size = ilog2(q->num_descs), |
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.q_init.ring_base = cpu_to_le64(q->base_pa), |
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.q_init.cq_ring_base = cpu_to_le64(cq->base_pa), |
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}; |
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ionic_dev_cmd_go(idev, &cmd); |
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} |
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int ionic_db_page_num(struct ionic_lif *lif, int pid) |
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{ |
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return (lif->hw_index * lif->dbid_count) + pid; |
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} |
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int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, |
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struct ionic_intr_info *intr, |
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unsigned int num_descs, size_t desc_size) |
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{ |
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unsigned int ring_size; |
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if (desc_size == 0 || !is_power_of_2(num_descs)) |
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return -EINVAL; |
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ring_size = ilog2(num_descs); |
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if (ring_size < 2 || ring_size > 16) |
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return -EINVAL; |
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cq->lif = lif; |
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cq->bound_intr = intr; |
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cq->num_descs = num_descs; |
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cq->desc_size = desc_size; |
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cq->tail_idx = 0; |
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cq->done_color = 1; |
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return 0; |
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} |
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void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa) |
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{ |
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struct ionic_cq_info *cur; |
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unsigned int i; |
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cq->base = base; |
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cq->base_pa = base_pa; |
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for (i = 0, cur = cq->info; i < cq->num_descs; i++, cur++) |
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cur->cq_desc = base + (i * cq->desc_size); |
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} |
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void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q) |
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{ |
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cq->bound_q = q; |
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} |
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unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do, |
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ionic_cq_cb cb, ionic_cq_done_cb done_cb, |
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void *done_arg) |
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{ |
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struct ionic_cq_info *cq_info; |
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unsigned int work_done = 0; |
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if (work_to_do == 0) |
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return 0; |
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cq_info = &cq->info[cq->tail_idx]; |
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while (cb(cq, cq_info)) { |
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if (cq->tail_idx == cq->num_descs - 1) |
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cq->done_color = !cq->done_color; |
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cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1); |
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cq_info = &cq->info[cq->tail_idx]; |
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DEBUG_STATS_CQE_CNT(cq); |
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if (++work_done >= work_to_do) |
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break; |
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} |
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if (work_done && done_cb) |
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done_cb(done_arg); |
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return work_done; |
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} |
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int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, |
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struct ionic_queue *q, unsigned int index, const char *name, |
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unsigned int num_descs, size_t desc_size, |
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size_t sg_desc_size, unsigned int pid) |
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{ |
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unsigned int ring_size; |
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if (desc_size == 0 || !is_power_of_2(num_descs)) |
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return -EINVAL; |
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ring_size = ilog2(num_descs); |
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if (ring_size < 2 || ring_size > 16) |
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return -EINVAL; |
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q->lif = lif; |
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q->idev = idev; |
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q->index = index; |
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q->num_descs = num_descs; |
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q->desc_size = desc_size; |
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q->sg_desc_size = sg_desc_size; |
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q->tail_idx = 0; |
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q->head_idx = 0; |
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q->pid = pid; |
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snprintf(q->name, sizeof(q->name), "L%d-%s%u", lif->index, name, index); |
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return 0; |
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} |
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void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) |
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{ |
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struct ionic_desc_info *cur; |
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unsigned int i; |
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q->base = base; |
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q->base_pa = base_pa; |
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for (i = 0, cur = q->info; i < q->num_descs; i++, cur++) |
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cur->desc = base + (i * q->desc_size); |
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} |
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void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) |
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{ |
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struct ionic_desc_info *cur; |
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unsigned int i; |
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q->sg_base = base; |
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q->sg_base_pa = base_pa; |
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for (i = 0, cur = q->info; i < q->num_descs; i++, cur++) |
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cur->sg_desc = base + (i * q->sg_desc_size); |
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} |
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void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb, |
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void *cb_arg) |
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{ |
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struct device *dev = q->lif->ionic->dev; |
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struct ionic_desc_info *desc_info; |
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struct ionic_lif *lif = q->lif; |
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desc_info = &q->info[q->head_idx]; |
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desc_info->cb = cb; |
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desc_info->cb_arg = cb_arg; |
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q->head_idx = (q->head_idx + 1) & (q->num_descs - 1); |
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dev_dbg(dev, "lif=%d qname=%s qid=%d qtype=%d p_index=%d ringdb=%d\n", |
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q->lif->index, q->name, q->hw_type, q->hw_index, |
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q->head_idx, ring_doorbell); |
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if (ring_doorbell) |
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ionic_dbell_ring(lif->kern_dbpage, q->hw_type, |
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q->dbval | q->head_idx); |
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} |
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static bool ionic_q_is_posted(struct ionic_queue *q, unsigned int pos) |
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{ |
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unsigned int mask, tail, head; |
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mask = q->num_descs - 1; |
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tail = q->tail_idx; |
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head = q->head_idx; |
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return ((pos - tail) & mask) < ((head - tail) & mask); |
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} |
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void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info, |
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unsigned int stop_index) |
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{ |
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struct ionic_desc_info *desc_info; |
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ionic_desc_cb cb; |
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void *cb_arg; |
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u16 index; |
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|
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/* check for empty queue */ |
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if (q->tail_idx == q->head_idx) |
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return; |
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|
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/* stop index must be for a descriptor that is not yet completed */ |
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if (unlikely(!ionic_q_is_posted(q, stop_index))) |
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dev_err(q->lif->ionic->dev, |
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"ionic stop is not posted %s stop %u tail %u head %u\n", |
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q->name, stop_index, q->tail_idx, q->head_idx); |
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do { |
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desc_info = &q->info[q->tail_idx]; |
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index = q->tail_idx; |
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q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); |
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cb = desc_info->cb; |
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cb_arg = desc_info->cb_arg; |
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desc_info->cb = NULL; |
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desc_info->cb_arg = NULL; |
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if (cb) |
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cb(q, desc_info, cq_info, cb_arg); |
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} while (index != stop_index); |
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}
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