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864 lines
21 KiB
864 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/** |
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* intel-pasid.c - PASID idr, table and entry manipulation |
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* |
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* Copyright (C) 2018 Intel Corporation |
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* |
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* Author: Lu Baolu <[email protected]> |
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*/ |
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|
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#define pr_fmt(fmt) "DMAR: " fmt |
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#include <linux/bitops.h> |
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#include <linux/cpufeature.h> |
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#include <linux/dmar.h> |
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#include <linux/intel-iommu.h> |
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#include <linux/iommu.h> |
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#include <linux/memory.h> |
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#include <linux/pci.h> |
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#include <linux/pci-ats.h> |
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#include <linux/spinlock.h> |
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#include "pasid.h" |
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/* |
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* Intel IOMMU system wide PASID name space: |
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*/ |
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static DEFINE_SPINLOCK(pasid_lock); |
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u32 intel_pasid_max_id = PASID_MAX; |
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int vcmd_alloc_pasid(struct intel_iommu *iommu, u32 *pasid) |
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{ |
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unsigned long flags; |
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u8 status_code; |
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int ret = 0; |
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u64 res; |
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raw_spin_lock_irqsave(&iommu->register_lock, flags); |
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dmar_writeq(iommu->reg + DMAR_VCMD_REG, VCMD_CMD_ALLOC); |
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IOMMU_WAIT_OP(iommu, DMAR_VCRSP_REG, dmar_readq, |
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!(res & VCMD_VRSP_IP), res); |
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raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
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status_code = VCMD_VRSP_SC(res); |
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switch (status_code) { |
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case VCMD_VRSP_SC_SUCCESS: |
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*pasid = VCMD_VRSP_RESULT_PASID(res); |
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break; |
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case VCMD_VRSP_SC_NO_PASID_AVAIL: |
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pr_info("IOMMU: %s: No PASID available\n", iommu->name); |
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ret = -ENOSPC; |
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break; |
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default: |
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ret = -ENODEV; |
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pr_warn("IOMMU: %s: Unexpected error code %d\n", |
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iommu->name, status_code); |
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} |
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return ret; |
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} |
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void vcmd_free_pasid(struct intel_iommu *iommu, u32 pasid) |
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{ |
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unsigned long flags; |
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u8 status_code; |
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u64 res; |
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raw_spin_lock_irqsave(&iommu->register_lock, flags); |
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dmar_writeq(iommu->reg + DMAR_VCMD_REG, |
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VCMD_CMD_OPERAND(pasid) | VCMD_CMD_FREE); |
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IOMMU_WAIT_OP(iommu, DMAR_VCRSP_REG, dmar_readq, |
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!(res & VCMD_VRSP_IP), res); |
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raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
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status_code = VCMD_VRSP_SC(res); |
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switch (status_code) { |
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case VCMD_VRSP_SC_SUCCESS: |
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break; |
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case VCMD_VRSP_SC_INVALID_PASID: |
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pr_info("IOMMU: %s: Invalid PASID\n", iommu->name); |
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break; |
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default: |
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pr_warn("IOMMU: %s: Unexpected error code %d\n", |
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iommu->name, status_code); |
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} |
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} |
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/* |
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* Per device pasid table management: |
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*/ |
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static inline void |
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device_attach_pasid_table(struct device_domain_info *info, |
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struct pasid_table *pasid_table) |
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{ |
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info->pasid_table = pasid_table; |
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list_add(&info->table, &pasid_table->dev); |
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} |
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static inline void |
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device_detach_pasid_table(struct device_domain_info *info, |
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struct pasid_table *pasid_table) |
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{ |
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info->pasid_table = NULL; |
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list_del(&info->table); |
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} |
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struct pasid_table_opaque { |
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struct pasid_table **pasid_table; |
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int segment; |
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int bus; |
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int devfn; |
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}; |
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static int search_pasid_table(struct device_domain_info *info, void *opaque) |
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{ |
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struct pasid_table_opaque *data = opaque; |
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if (info->iommu->segment == data->segment && |
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info->bus == data->bus && |
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info->devfn == data->devfn && |
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info->pasid_table) { |
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*data->pasid_table = info->pasid_table; |
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return 1; |
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} |
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return 0; |
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} |
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static int get_alias_pasid_table(struct pci_dev *pdev, u16 alias, void *opaque) |
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{ |
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struct pasid_table_opaque *data = opaque; |
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data->segment = pci_domain_nr(pdev->bus); |
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data->bus = PCI_BUS_NUM(alias); |
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data->devfn = alias & 0xff; |
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return for_each_device_domain(&search_pasid_table, data); |
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} |
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/* |
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* Allocate a pasid table for @dev. It should be called in a |
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* single-thread context. |
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*/ |
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int intel_pasid_alloc_table(struct device *dev) |
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{ |
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struct device_domain_info *info; |
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struct pasid_table *pasid_table; |
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struct pasid_table_opaque data; |
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struct page *pages; |
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u32 max_pasid = 0; |
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int ret, order; |
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int size; |
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might_sleep(); |
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info = get_domain_info(dev); |
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if (WARN_ON(!info || !dev_is_pci(dev) || info->pasid_table)) |
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return -EINVAL; |
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/* DMA alias device already has a pasid table, use it: */ |
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data.pasid_table = &pasid_table; |
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ret = pci_for_each_dma_alias(to_pci_dev(dev), |
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&get_alias_pasid_table, &data); |
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if (ret) |
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goto attach_out; |
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pasid_table = kzalloc(sizeof(*pasid_table), GFP_KERNEL); |
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if (!pasid_table) |
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return -ENOMEM; |
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INIT_LIST_HEAD(&pasid_table->dev); |
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if (info->pasid_supported) |
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max_pasid = min_t(u32, pci_max_pasids(to_pci_dev(dev)), |
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intel_pasid_max_id); |
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size = max_pasid >> (PASID_PDE_SHIFT - 3); |
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order = size ? get_order(size) : 0; |
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pages = alloc_pages_node(info->iommu->node, |
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GFP_KERNEL | __GFP_ZERO, order); |
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if (!pages) { |
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kfree(pasid_table); |
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return -ENOMEM; |
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} |
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pasid_table->table = page_address(pages); |
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pasid_table->order = order; |
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pasid_table->max_pasid = 1 << (order + PAGE_SHIFT + 3); |
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attach_out: |
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device_attach_pasid_table(info, pasid_table); |
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return 0; |
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} |
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void intel_pasid_free_table(struct device *dev) |
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{ |
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struct device_domain_info *info; |
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struct pasid_table *pasid_table; |
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struct pasid_dir_entry *dir; |
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struct pasid_entry *table; |
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int i, max_pde; |
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info = get_domain_info(dev); |
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if (!info || !dev_is_pci(dev) || !info->pasid_table) |
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return; |
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pasid_table = info->pasid_table; |
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device_detach_pasid_table(info, pasid_table); |
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if (!list_empty(&pasid_table->dev)) |
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return; |
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/* Free scalable mode PASID directory tables: */ |
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dir = pasid_table->table; |
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max_pde = pasid_table->max_pasid >> PASID_PDE_SHIFT; |
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for (i = 0; i < max_pde; i++) { |
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table = get_pasid_table_from_pde(&dir[i]); |
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free_pgtable_page(table); |
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} |
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free_pages((unsigned long)pasid_table->table, pasid_table->order); |
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kfree(pasid_table); |
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} |
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struct pasid_table *intel_pasid_get_table(struct device *dev) |
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{ |
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struct device_domain_info *info; |
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info = get_domain_info(dev); |
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if (!info) |
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return NULL; |
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return info->pasid_table; |
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} |
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int intel_pasid_get_dev_max_id(struct device *dev) |
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{ |
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struct device_domain_info *info; |
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info = get_domain_info(dev); |
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if (!info || !info->pasid_table) |
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return 0; |
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return info->pasid_table->max_pasid; |
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} |
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struct pasid_entry *intel_pasid_get_entry(struct device *dev, u32 pasid) |
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{ |
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struct device_domain_info *info; |
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struct pasid_table *pasid_table; |
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struct pasid_dir_entry *dir; |
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struct pasid_entry *entries; |
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int dir_index, index; |
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pasid_table = intel_pasid_get_table(dev); |
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if (WARN_ON(!pasid_table || pasid >= intel_pasid_get_dev_max_id(dev))) |
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return NULL; |
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dir = pasid_table->table; |
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info = get_domain_info(dev); |
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dir_index = pasid >> PASID_PDE_SHIFT; |
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index = pasid & PASID_PTE_MASK; |
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spin_lock(&pasid_lock); |
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entries = get_pasid_table_from_pde(&dir[dir_index]); |
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if (!entries) { |
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entries = alloc_pgtable_page(info->iommu->node); |
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if (!entries) { |
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spin_unlock(&pasid_lock); |
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return NULL; |
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} |
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WRITE_ONCE(dir[dir_index].val, |
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(u64)virt_to_phys(entries) | PASID_PTE_PRESENT); |
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} |
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spin_unlock(&pasid_lock); |
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return &entries[index]; |
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} |
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/* |
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* Interfaces for PASID table entry manipulation: |
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*/ |
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static inline void pasid_clear_entry(struct pasid_entry *pe) |
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{ |
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WRITE_ONCE(pe->val[0], 0); |
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WRITE_ONCE(pe->val[1], 0); |
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WRITE_ONCE(pe->val[2], 0); |
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WRITE_ONCE(pe->val[3], 0); |
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WRITE_ONCE(pe->val[4], 0); |
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WRITE_ONCE(pe->val[5], 0); |
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WRITE_ONCE(pe->val[6], 0); |
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WRITE_ONCE(pe->val[7], 0); |
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} |
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static inline void pasid_clear_entry_with_fpd(struct pasid_entry *pe) |
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{ |
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WRITE_ONCE(pe->val[0], PASID_PTE_FPD); |
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WRITE_ONCE(pe->val[1], 0); |
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WRITE_ONCE(pe->val[2], 0); |
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WRITE_ONCE(pe->val[3], 0); |
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WRITE_ONCE(pe->val[4], 0); |
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WRITE_ONCE(pe->val[5], 0); |
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WRITE_ONCE(pe->val[6], 0); |
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WRITE_ONCE(pe->val[7], 0); |
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} |
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static void |
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intel_pasid_clear_entry(struct device *dev, u32 pasid, bool fault_ignore) |
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{ |
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struct pasid_entry *pe; |
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pe = intel_pasid_get_entry(dev, pasid); |
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if (WARN_ON(!pe)) |
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return; |
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if (fault_ignore && pasid_pte_is_present(pe)) |
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pasid_clear_entry_with_fpd(pe); |
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else |
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pasid_clear_entry(pe); |
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} |
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static inline void pasid_set_bits(u64 *ptr, u64 mask, u64 bits) |
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{ |
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u64 old; |
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old = READ_ONCE(*ptr); |
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WRITE_ONCE(*ptr, (old & ~mask) | bits); |
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} |
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/* |
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* Setup the DID(Domain Identifier) field (Bit 64~79) of scalable mode |
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* PASID entry. |
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*/ |
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static inline void |
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pasid_set_domain_id(struct pasid_entry *pe, u64 value) |
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{ |
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pasid_set_bits(&pe->val[1], GENMASK_ULL(15, 0), value); |
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} |
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/* |
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* Get domain ID value of a scalable mode PASID entry. |
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*/ |
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static inline u16 |
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pasid_get_domain_id(struct pasid_entry *pe) |
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{ |
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return (u16)(READ_ONCE(pe->val[1]) & GENMASK_ULL(15, 0)); |
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} |
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/* |
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* Setup the SLPTPTR(Second Level Page Table Pointer) field (Bit 12~63) |
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* of a scalable mode PASID entry. |
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*/ |
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static inline void |
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pasid_set_slptr(struct pasid_entry *pe, u64 value) |
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{ |
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pasid_set_bits(&pe->val[0], VTD_PAGE_MASK, value); |
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} |
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/* |
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* Setup the AW(Address Width) field (Bit 2~4) of a scalable mode PASID |
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* entry. |
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*/ |
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static inline void |
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pasid_set_address_width(struct pasid_entry *pe, u64 value) |
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{ |
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pasid_set_bits(&pe->val[0], GENMASK_ULL(4, 2), value << 2); |
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} |
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/* |
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* Setup the PGTT(PASID Granular Translation Type) field (Bit 6~8) |
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* of a scalable mode PASID entry. |
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*/ |
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static inline void |
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pasid_set_translation_type(struct pasid_entry *pe, u64 value) |
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{ |
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pasid_set_bits(&pe->val[0], GENMASK_ULL(8, 6), value << 6); |
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} |
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/* |
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* Enable fault processing by clearing the FPD(Fault Processing |
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* Disable) field (Bit 1) of a scalable mode PASID entry. |
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*/ |
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static inline void pasid_set_fault_enable(struct pasid_entry *pe) |
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{ |
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pasid_set_bits(&pe->val[0], 1 << 1, 0); |
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} |
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/* |
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* Setup the SRE(Supervisor Request Enable) field (Bit 128) of a |
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* scalable mode PASID entry. |
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*/ |
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static inline void pasid_set_sre(struct pasid_entry *pe) |
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{ |
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pasid_set_bits(&pe->val[2], 1 << 0, 1); |
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} |
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/* |
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* Setup the P(Present) field (Bit 0) of a scalable mode PASID |
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* entry. |
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*/ |
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static inline void pasid_set_present(struct pasid_entry *pe) |
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{ |
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pasid_set_bits(&pe->val[0], 1 << 0, 1); |
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} |
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/* |
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* Setup Page Walk Snoop bit (Bit 87) of a scalable mode PASID |
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* entry. |
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*/ |
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static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value) |
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{ |
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pasid_set_bits(&pe->val[1], 1 << 23, value << 23); |
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} |
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/* |
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* Setup the Page Snoop (PGSNP) field (Bit 88) of a scalable mode |
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* PASID entry. |
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*/ |
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static inline void |
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pasid_set_pgsnp(struct pasid_entry *pe) |
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{ |
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pasid_set_bits(&pe->val[1], 1ULL << 24, 1ULL << 24); |
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} |
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/* |
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* Setup the First Level Page table Pointer field (Bit 140~191) |
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* of a scalable mode PASID entry. |
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*/ |
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static inline void |
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pasid_set_flptr(struct pasid_entry *pe, u64 value) |
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{ |
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pasid_set_bits(&pe->val[2], VTD_PAGE_MASK, value); |
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} |
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/* |
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* Setup the First Level Paging Mode field (Bit 130~131) of a |
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* scalable mode PASID entry. |
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*/ |
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static inline void |
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pasid_set_flpm(struct pasid_entry *pe, u64 value) |
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{ |
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pasid_set_bits(&pe->val[2], GENMASK_ULL(3, 2), value << 2); |
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} |
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/* |
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* Setup the Extended Access Flag Enable (EAFE) field (Bit 135) |
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* of a scalable mode PASID entry. |
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*/ |
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static inline void |
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pasid_set_eafe(struct pasid_entry *pe) |
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{ |
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pasid_set_bits(&pe->val[2], 1 << 7, 1 << 7); |
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} |
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static void |
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pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu, |
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u16 did, u32 pasid) |
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{ |
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struct qi_desc desc; |
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desc.qw0 = QI_PC_DID(did) | QI_PC_GRAN(QI_PC_PASID_SEL) | |
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QI_PC_PASID(pasid) | QI_PC_TYPE; |
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desc.qw1 = 0; |
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desc.qw2 = 0; |
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desc.qw3 = 0; |
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qi_submit_sync(iommu, &desc, 1, 0); |
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} |
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static void |
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devtlb_invalidation_with_pasid(struct intel_iommu *iommu, |
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struct device *dev, u32 pasid) |
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{ |
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struct device_domain_info *info; |
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u16 sid, qdep, pfsid; |
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info = get_domain_info(dev); |
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if (!info || !info->ats_enabled) |
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return; |
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sid = info->bus << 8 | info->devfn; |
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qdep = info->ats_qdep; |
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pfsid = info->pfsid; |
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/* |
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* When PASID 0 is used, it indicates RID2PASID(DMA request w/o PASID), |
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* devTLB flush w/o PASID should be used. For non-zero PASID under |
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* SVA usage, device could do DMA with multiple PASIDs. It is more |
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* efficient to flush devTLB specific to the PASID. |
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*/ |
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if (pasid == PASID_RID2PASID) |
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qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT); |
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else |
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qi_flush_dev_iotlb_pasid(iommu, sid, pfsid, pasid, qdep, 0, 64 - VTD_PAGE_SHIFT); |
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} |
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void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, |
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u32 pasid, bool fault_ignore) |
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{ |
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struct pasid_entry *pte; |
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u16 did; |
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pte = intel_pasid_get_entry(dev, pasid); |
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if (WARN_ON(!pte)) |
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return; |
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did = pasid_get_domain_id(pte); |
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intel_pasid_clear_entry(dev, pasid, fault_ignore); |
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|
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if (!ecap_coherent(iommu->ecap)) |
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clflush_cache_range(pte, sizeof(*pte)); |
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pasid_cache_invalidation_with_pasid(iommu, did, pasid); |
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qi_flush_piotlb(iommu, did, pasid, 0, -1, 0); |
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/* Device IOTLB doesn't need to be flushed in caching mode. */ |
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if (!cap_caching_mode(iommu->cap)) |
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devtlb_invalidation_with_pasid(iommu, dev, pasid); |
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} |
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static void pasid_flush_caches(struct intel_iommu *iommu, |
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struct pasid_entry *pte, |
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u32 pasid, u16 did) |
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{ |
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if (!ecap_coherent(iommu->ecap)) |
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clflush_cache_range(pte, sizeof(*pte)); |
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if (cap_caching_mode(iommu->cap)) { |
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pasid_cache_invalidation_with_pasid(iommu, did, pasid); |
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qi_flush_piotlb(iommu, did, pasid, 0, -1, 0); |
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} else { |
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iommu_flush_write_buffer(iommu); |
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} |
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} |
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/* |
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* Set up the scalable mode pasid table entry for first only |
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* translation type. |
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*/ |
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int intel_pasid_setup_first_level(struct intel_iommu *iommu, |
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struct device *dev, pgd_t *pgd, |
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u32 pasid, u16 did, int flags) |
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{ |
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struct pasid_entry *pte; |
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if (!ecap_flts(iommu->ecap)) { |
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pr_err("No first level translation support on %s\n", |
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iommu->name); |
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return -EINVAL; |
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} |
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pte = intel_pasid_get_entry(dev, pasid); |
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if (WARN_ON(!pte)) |
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return -EINVAL; |
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pasid_clear_entry(pte); |
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/* Setup the first level page table pointer: */ |
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pasid_set_flptr(pte, (u64)__pa(pgd)); |
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if (flags & PASID_FLAG_SUPERVISOR_MODE) { |
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if (!ecap_srs(iommu->ecap)) { |
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pr_err("No supervisor request support on %s\n", |
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iommu->name); |
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return -EINVAL; |
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} |
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pasid_set_sre(pte); |
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} |
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|
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if (flags & PASID_FLAG_FL5LP) { |
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if (cap_5lp_support(iommu->cap)) { |
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pasid_set_flpm(pte, 1); |
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} else { |
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pr_err("No 5-level paging support for first-level\n"); |
|
pasid_clear_entry(pte); |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
if (flags & PASID_FLAG_PAGE_SNOOP) |
|
pasid_set_pgsnp(pte); |
|
|
|
pasid_set_domain_id(pte, did); |
|
pasid_set_address_width(pte, iommu->agaw); |
|
pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap)); |
|
|
|
/* Setup Present and PASID Granular Transfer Type: */ |
|
pasid_set_translation_type(pte, PASID_ENTRY_PGTT_FL_ONLY); |
|
pasid_set_present(pte); |
|
pasid_flush_caches(iommu, pte, pasid, did); |
|
|
|
return 0; |
|
} |
|
|
|
/* |
|
* Skip top levels of page tables for iommu which has less agaw |
|
* than default. Unnecessary for PT mode. |
|
*/ |
|
static inline int iommu_skip_agaw(struct dmar_domain *domain, |
|
struct intel_iommu *iommu, |
|
struct dma_pte **pgd) |
|
{ |
|
int agaw; |
|
|
|
for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) { |
|
*pgd = phys_to_virt(dma_pte_addr(*pgd)); |
|
if (!dma_pte_present(*pgd)) |
|
return -EINVAL; |
|
} |
|
|
|
return agaw; |
|
} |
|
|
|
/* |
|
* Set up the scalable mode pasid entry for second only translation type. |
|
*/ |
|
int intel_pasid_setup_second_level(struct intel_iommu *iommu, |
|
struct dmar_domain *domain, |
|
struct device *dev, u32 pasid) |
|
{ |
|
struct pasid_entry *pte; |
|
struct dma_pte *pgd; |
|
u64 pgd_val; |
|
int agaw; |
|
u16 did; |
|
|
|
/* |
|
* If hardware advertises no support for second level |
|
* translation, return directly. |
|
*/ |
|
if (!ecap_slts(iommu->ecap)) { |
|
pr_err("No second level translation support on %s\n", |
|
iommu->name); |
|
return -EINVAL; |
|
} |
|
|
|
pgd = domain->pgd; |
|
agaw = iommu_skip_agaw(domain, iommu, &pgd); |
|
if (agaw < 0) { |
|
dev_err(dev, "Invalid domain page table\n"); |
|
return -EINVAL; |
|
} |
|
|
|
pgd_val = virt_to_phys(pgd); |
|
did = domain->iommu_did[iommu->seq_id]; |
|
|
|
pte = intel_pasid_get_entry(dev, pasid); |
|
if (!pte) { |
|
dev_err(dev, "Failed to get pasid entry of PASID %d\n", pasid); |
|
return -ENODEV; |
|
} |
|
|
|
pasid_clear_entry(pte); |
|
pasid_set_domain_id(pte, did); |
|
pasid_set_slptr(pte, pgd_val); |
|
pasid_set_address_width(pte, agaw); |
|
pasid_set_translation_type(pte, PASID_ENTRY_PGTT_SL_ONLY); |
|
pasid_set_fault_enable(pte); |
|
pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap)); |
|
|
|
if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED) |
|
pasid_set_pgsnp(pte); |
|
|
|
/* |
|
* Since it is a second level only translation setup, we should |
|
* set SRE bit as well (addresses are expected to be GPAs). |
|
*/ |
|
if (pasid != PASID_RID2PASID) |
|
pasid_set_sre(pte); |
|
pasid_set_present(pte); |
|
pasid_flush_caches(iommu, pte, pasid, did); |
|
|
|
return 0; |
|
} |
|
|
|
/* |
|
* Set up the scalable mode pasid entry for passthrough translation type. |
|
*/ |
|
int intel_pasid_setup_pass_through(struct intel_iommu *iommu, |
|
struct dmar_domain *domain, |
|
struct device *dev, u32 pasid) |
|
{ |
|
u16 did = FLPT_DEFAULT_DID; |
|
struct pasid_entry *pte; |
|
|
|
pte = intel_pasid_get_entry(dev, pasid); |
|
if (!pte) { |
|
dev_err(dev, "Failed to get pasid entry of PASID %d\n", pasid); |
|
return -ENODEV; |
|
} |
|
|
|
pasid_clear_entry(pte); |
|
pasid_set_domain_id(pte, did); |
|
pasid_set_address_width(pte, iommu->agaw); |
|
pasid_set_translation_type(pte, PASID_ENTRY_PGTT_PT); |
|
pasid_set_fault_enable(pte); |
|
pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap)); |
|
|
|
/* |
|
* We should set SRE bit as well since the addresses are expected |
|
* to be GPAs. |
|
*/ |
|
pasid_set_sre(pte); |
|
pasid_set_present(pte); |
|
pasid_flush_caches(iommu, pte, pasid, did); |
|
|
|
return 0; |
|
} |
|
|
|
static int |
|
intel_pasid_setup_bind_data(struct intel_iommu *iommu, struct pasid_entry *pte, |
|
struct iommu_gpasid_bind_data_vtd *pasid_data) |
|
{ |
|
/* |
|
* Not all guest PASID table entry fields are passed down during bind, |
|
* here we only set up the ones that are dependent on guest settings. |
|
* Execution related bits such as NXE, SMEP are not supported. |
|
* Other fields, such as snoop related, are set based on host needs |
|
* regardless of guest settings. |
|
*/ |
|
if (pasid_data->flags & IOMMU_SVA_VTD_GPASID_SRE) { |
|
if (!ecap_srs(iommu->ecap)) { |
|
pr_err_ratelimited("No supervisor request support on %s\n", |
|
iommu->name); |
|
return -EINVAL; |
|
} |
|
pasid_set_sre(pte); |
|
} |
|
|
|
if (pasid_data->flags & IOMMU_SVA_VTD_GPASID_EAFE) { |
|
if (!ecap_eafs(iommu->ecap)) { |
|
pr_err_ratelimited("No extended access flag support on %s\n", |
|
iommu->name); |
|
return -EINVAL; |
|
} |
|
pasid_set_eafe(pte); |
|
} |
|
|
|
/* |
|
* Memory type is only applicable to devices inside processor coherent |
|
* domain. Will add MTS support once coherent devices are available. |
|
*/ |
|
if (pasid_data->flags & IOMMU_SVA_VTD_GPASID_MTS_MASK) { |
|
pr_warn_ratelimited("No memory type support %s\n", |
|
iommu->name); |
|
return -EINVAL; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* intel_pasid_setup_nested() - Set up PASID entry for nested translation. |
|
* This could be used for guest shared virtual address. In this case, the |
|
* first level page tables are used for GVA-GPA translation in the guest, |
|
* second level page tables are used for GPA-HPA translation. |
|
* |
|
* @iommu: IOMMU which the device belong to |
|
* @dev: Device to be set up for translation |
|
* @gpgd: FLPTPTR: First Level Page translation pointer in GPA |
|
* @pasid: PASID to be programmed in the device PASID table |
|
* @pasid_data: Additional PASID info from the guest bind request |
|
* @domain: Domain info for setting up second level page tables |
|
* @addr_width: Address width of the first level (guest) |
|
*/ |
|
int intel_pasid_setup_nested(struct intel_iommu *iommu, struct device *dev, |
|
pgd_t *gpgd, u32 pasid, |
|
struct iommu_gpasid_bind_data_vtd *pasid_data, |
|
struct dmar_domain *domain, int addr_width) |
|
{ |
|
struct pasid_entry *pte; |
|
struct dma_pte *pgd; |
|
int ret = 0; |
|
u64 pgd_val; |
|
int agaw; |
|
u16 did; |
|
|
|
if (!ecap_nest(iommu->ecap)) { |
|
pr_err_ratelimited("IOMMU: %s: No nested translation support\n", |
|
iommu->name); |
|
return -EINVAL; |
|
} |
|
|
|
if (!(domain->flags & DOMAIN_FLAG_NESTING_MODE)) { |
|
pr_err_ratelimited("Domain is not in nesting mode, %x\n", |
|
domain->flags); |
|
return -EINVAL; |
|
} |
|
|
|
pte = intel_pasid_get_entry(dev, pasid); |
|
if (WARN_ON(!pte)) |
|
return -EINVAL; |
|
|
|
/* |
|
* Caller must ensure PASID entry is not in use, i.e. not bind the |
|
* same PASID to the same device twice. |
|
*/ |
|
if (pasid_pte_is_present(pte)) |
|
return -EBUSY; |
|
|
|
pasid_clear_entry(pte); |
|
|
|
/* Sanity checking performed by caller to make sure address |
|
* width matching in two dimensions: |
|
* 1. CPU vs. IOMMU |
|
* 2. Guest vs. Host. |
|
*/ |
|
switch (addr_width) { |
|
#ifdef CONFIG_X86 |
|
case ADDR_WIDTH_5LEVEL: |
|
if (!cpu_feature_enabled(X86_FEATURE_LA57) || |
|
!cap_5lp_support(iommu->cap)) { |
|
dev_err_ratelimited(dev, |
|
"5-level paging not supported\n"); |
|
return -EINVAL; |
|
} |
|
|
|
pasid_set_flpm(pte, 1); |
|
break; |
|
#endif |
|
case ADDR_WIDTH_4LEVEL: |
|
pasid_set_flpm(pte, 0); |
|
break; |
|
default: |
|
dev_err_ratelimited(dev, "Invalid guest address width %d\n", |
|
addr_width); |
|
return -EINVAL; |
|
} |
|
|
|
/* First level PGD is in GPA, must be supported by the second level */ |
|
if ((uintptr_t)gpgd > domain->max_addr) { |
|
dev_err_ratelimited(dev, |
|
"Guest PGD %lx not supported, max %llx\n", |
|
(uintptr_t)gpgd, domain->max_addr); |
|
return -EINVAL; |
|
} |
|
pasid_set_flptr(pte, (uintptr_t)gpgd); |
|
|
|
ret = intel_pasid_setup_bind_data(iommu, pte, pasid_data); |
|
if (ret) |
|
return ret; |
|
|
|
/* Setup the second level based on the given domain */ |
|
pgd = domain->pgd; |
|
|
|
agaw = iommu_skip_agaw(domain, iommu, &pgd); |
|
if (agaw < 0) { |
|
dev_err_ratelimited(dev, "Invalid domain page table\n"); |
|
return -EINVAL; |
|
} |
|
pgd_val = virt_to_phys(pgd); |
|
pasid_set_slptr(pte, pgd_val); |
|
pasid_set_fault_enable(pte); |
|
|
|
did = domain->iommu_did[iommu->seq_id]; |
|
pasid_set_domain_id(pte, did); |
|
|
|
pasid_set_address_width(pte, agaw); |
|
pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap)); |
|
|
|
pasid_set_translation_type(pte, PASID_ENTRY_PGTT_NESTED); |
|
pasid_set_present(pte); |
|
pasid_flush_caches(iommu, pte, pasid, did); |
|
|
|
return ret; |
|
}
|
|
|