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559 lines
15 KiB
559 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright © 2018 Intel Corporation. |
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* |
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* Authors: Gayatri Kammela <[email protected]> |
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* Sohil Mehta <[email protected]> |
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* Jacob Pan <[email protected]> |
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* Lu Baolu <[email protected]> |
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*/ |
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|
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#include <linux/debugfs.h> |
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#include <linux/dmar.h> |
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#include <linux/intel-iommu.h> |
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#include <linux/pci.h> |
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|
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#include <asm/irq_remapping.h> |
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#include "pasid.h" |
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|
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struct tbl_walk { |
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u16 bus; |
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u16 devfn; |
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u32 pasid; |
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struct root_entry *rt_entry; |
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struct context_entry *ctx_entry; |
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struct pasid_entry *pasid_tbl_entry; |
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}; |
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struct iommu_regset { |
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int offset; |
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const char *regs; |
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}; |
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#define IOMMU_REGSET_ENTRY(_reg_) \ |
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{ DMAR_##_reg_##_REG, __stringify(_reg_) } |
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static const struct iommu_regset iommu_regs_32[] = { |
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IOMMU_REGSET_ENTRY(VER), |
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IOMMU_REGSET_ENTRY(GCMD), |
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IOMMU_REGSET_ENTRY(GSTS), |
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IOMMU_REGSET_ENTRY(FSTS), |
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IOMMU_REGSET_ENTRY(FECTL), |
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IOMMU_REGSET_ENTRY(FEDATA), |
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IOMMU_REGSET_ENTRY(FEADDR), |
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IOMMU_REGSET_ENTRY(FEUADDR), |
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IOMMU_REGSET_ENTRY(PMEN), |
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IOMMU_REGSET_ENTRY(PLMBASE), |
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IOMMU_REGSET_ENTRY(PLMLIMIT), |
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IOMMU_REGSET_ENTRY(ICS), |
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IOMMU_REGSET_ENTRY(PRS), |
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IOMMU_REGSET_ENTRY(PECTL), |
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IOMMU_REGSET_ENTRY(PEDATA), |
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IOMMU_REGSET_ENTRY(PEADDR), |
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IOMMU_REGSET_ENTRY(PEUADDR), |
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}; |
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static const struct iommu_regset iommu_regs_64[] = { |
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IOMMU_REGSET_ENTRY(CAP), |
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IOMMU_REGSET_ENTRY(ECAP), |
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IOMMU_REGSET_ENTRY(RTADDR), |
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IOMMU_REGSET_ENTRY(CCMD), |
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IOMMU_REGSET_ENTRY(AFLOG), |
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IOMMU_REGSET_ENTRY(PHMBASE), |
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IOMMU_REGSET_ENTRY(PHMLIMIT), |
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IOMMU_REGSET_ENTRY(IQH), |
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IOMMU_REGSET_ENTRY(IQT), |
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IOMMU_REGSET_ENTRY(IQA), |
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IOMMU_REGSET_ENTRY(IRTA), |
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IOMMU_REGSET_ENTRY(PQH), |
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IOMMU_REGSET_ENTRY(PQT), |
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IOMMU_REGSET_ENTRY(PQA), |
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IOMMU_REGSET_ENTRY(MTRRCAP), |
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IOMMU_REGSET_ENTRY(MTRRDEF), |
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IOMMU_REGSET_ENTRY(MTRR_FIX64K_00000), |
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IOMMU_REGSET_ENTRY(MTRR_FIX16K_80000), |
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IOMMU_REGSET_ENTRY(MTRR_FIX16K_A0000), |
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_C0000), |
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_C8000), |
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_D0000), |
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_D8000), |
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_E0000), |
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_E8000), |
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_F0000), |
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_F8000), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE0), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK0), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE1), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK1), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE2), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK2), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE3), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK3), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE4), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK4), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE5), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK5), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE6), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK6), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE7), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK7), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE8), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK8), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE9), |
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK9), |
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IOMMU_REGSET_ENTRY(VCCAP), |
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IOMMU_REGSET_ENTRY(VCMD), |
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IOMMU_REGSET_ENTRY(VCRSP), |
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}; |
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static int iommu_regset_show(struct seq_file *m, void *unused) |
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{ |
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struct dmar_drhd_unit *drhd; |
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struct intel_iommu *iommu; |
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unsigned long flag; |
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int i, ret = 0; |
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u64 value; |
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rcu_read_lock(); |
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for_each_active_iommu(iommu, drhd) { |
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if (!drhd->reg_base_addr) { |
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seq_puts(m, "IOMMU: Invalid base address\n"); |
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ret = -EINVAL; |
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goto out; |
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} |
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seq_printf(m, "IOMMU: %s Register Base Address: %llx\n", |
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iommu->name, drhd->reg_base_addr); |
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seq_puts(m, "Name\t\t\tOffset\t\tContents\n"); |
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/* |
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* Publish the contents of the 64-bit hardware registers |
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* by adding the offset to the pointer (virtual address). |
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*/ |
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raw_spin_lock_irqsave(&iommu->register_lock, flag); |
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for (i = 0 ; i < ARRAY_SIZE(iommu_regs_32); i++) { |
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value = dmar_readl(iommu->reg + iommu_regs_32[i].offset); |
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seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n", |
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iommu_regs_32[i].regs, iommu_regs_32[i].offset, |
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value); |
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} |
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for (i = 0 ; i < ARRAY_SIZE(iommu_regs_64); i++) { |
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value = dmar_readq(iommu->reg + iommu_regs_64[i].offset); |
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seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n", |
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iommu_regs_64[i].regs, iommu_regs_64[i].offset, |
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value); |
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} |
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
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seq_putc(m, '\n'); |
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} |
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out: |
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rcu_read_unlock(); |
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return ret; |
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} |
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DEFINE_SHOW_ATTRIBUTE(iommu_regset); |
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static inline void print_tbl_walk(struct seq_file *m) |
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{ |
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struct tbl_walk *tbl_wlk = m->private; |
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seq_printf(m, "%02x:%02x.%x\t0x%016llx:0x%016llx\t0x%016llx:0x%016llx\t", |
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tbl_wlk->bus, PCI_SLOT(tbl_wlk->devfn), |
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PCI_FUNC(tbl_wlk->devfn), tbl_wlk->rt_entry->hi, |
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tbl_wlk->rt_entry->lo, tbl_wlk->ctx_entry->hi, |
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tbl_wlk->ctx_entry->lo); |
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/* |
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* A legacy mode DMAR doesn't support PASID, hence default it to -1 |
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* indicating that it's invalid. Also, default all PASID related fields |
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* to 0. |
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*/ |
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if (!tbl_wlk->pasid_tbl_entry) |
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seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", -1, |
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(u64)0, (u64)0, (u64)0); |
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else |
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seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", |
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tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2], |
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tbl_wlk->pasid_tbl_entry->val[1], |
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tbl_wlk->pasid_tbl_entry->val[0]); |
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} |
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static void pasid_tbl_walk(struct seq_file *m, struct pasid_entry *tbl_entry, |
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u16 dir_idx) |
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{ |
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struct tbl_walk *tbl_wlk = m->private; |
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u8 tbl_idx; |
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for (tbl_idx = 0; tbl_idx < PASID_TBL_ENTRIES; tbl_idx++) { |
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if (pasid_pte_is_present(tbl_entry)) { |
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tbl_wlk->pasid_tbl_entry = tbl_entry; |
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tbl_wlk->pasid = (dir_idx << PASID_PDE_SHIFT) + tbl_idx; |
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print_tbl_walk(m); |
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} |
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tbl_entry++; |
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} |
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} |
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static void pasid_dir_walk(struct seq_file *m, u64 pasid_dir_ptr, |
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u16 pasid_dir_size) |
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{ |
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struct pasid_dir_entry *dir_entry = phys_to_virt(pasid_dir_ptr); |
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struct pasid_entry *pasid_tbl; |
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u16 dir_idx; |
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for (dir_idx = 0; dir_idx < pasid_dir_size; dir_idx++) { |
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pasid_tbl = get_pasid_table_from_pde(dir_entry); |
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if (pasid_tbl) |
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pasid_tbl_walk(m, pasid_tbl, dir_idx); |
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dir_entry++; |
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} |
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} |
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static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus) |
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{ |
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struct context_entry *context; |
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u16 devfn, pasid_dir_size; |
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u64 pasid_dir_ptr; |
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for (devfn = 0; devfn < 256; devfn++) { |
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struct tbl_walk tbl_wlk = {0}; |
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/* |
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* Scalable mode root entry points to upper scalable mode |
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* context table and lower scalable mode context table. Each |
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* scalable mode context table has 128 context entries where as |
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* legacy mode context table has 256 context entries. So in |
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* scalable mode, the context entries for former 128 devices are |
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* in the lower scalable mode context table, while the latter |
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* 128 devices are in the upper scalable mode context table. |
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* In scalable mode, when devfn > 127, iommu_context_addr() |
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* automatically refers to upper scalable mode context table and |
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* hence the caller doesn't have to worry about differences |
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* between scalable mode and non scalable mode. |
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*/ |
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context = iommu_context_addr(iommu, bus, devfn, 0); |
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if (!context) |
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return; |
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if (!context_present(context)) |
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continue; |
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tbl_wlk.bus = bus; |
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tbl_wlk.devfn = devfn; |
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tbl_wlk.rt_entry = &iommu->root_entry[bus]; |
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tbl_wlk.ctx_entry = context; |
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m->private = &tbl_wlk; |
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if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) { |
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pasid_dir_ptr = context->lo & VTD_PAGE_MASK; |
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pasid_dir_size = get_pasid_dir_size(context); |
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pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size); |
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continue; |
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} |
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print_tbl_walk(m); |
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} |
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} |
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static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu) |
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{ |
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unsigned long flags; |
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u16 bus; |
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spin_lock_irqsave(&iommu->lock, flags); |
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seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name, |
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(u64)virt_to_phys(iommu->root_entry)); |
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seq_puts(m, "B.D.F\tRoot_entry\t\t\t\tContext_entry\t\t\t\tPASID\tPASID_table_entry\n"); |
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/* |
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* No need to check if the root entry is present or not because |
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* iommu_context_addr() performs the same check before returning |
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* context entry. |
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*/ |
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for (bus = 0; bus < 256; bus++) |
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ctx_tbl_walk(m, iommu, bus); |
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spin_unlock_irqrestore(&iommu->lock, flags); |
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} |
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static int dmar_translation_struct_show(struct seq_file *m, void *unused) |
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{ |
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struct dmar_drhd_unit *drhd; |
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struct intel_iommu *iommu; |
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u32 sts; |
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rcu_read_lock(); |
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for_each_active_iommu(iommu, drhd) { |
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sts = dmar_readl(iommu->reg + DMAR_GSTS_REG); |
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if (!(sts & DMA_GSTS_TES)) { |
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seq_printf(m, "DMA Remapping is not enabled on %s\n", |
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iommu->name); |
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continue; |
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} |
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root_tbl_walk(m, iommu); |
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seq_putc(m, '\n'); |
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} |
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rcu_read_unlock(); |
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return 0; |
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} |
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DEFINE_SHOW_ATTRIBUTE(dmar_translation_struct); |
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static inline unsigned long level_to_directory_size(int level) |
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{ |
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return BIT_ULL(VTD_PAGE_SHIFT + VTD_STRIDE_SHIFT * (level - 1)); |
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} |
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static inline void |
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dump_page_info(struct seq_file *m, unsigned long iova, u64 *path) |
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{ |
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seq_printf(m, "0x%013lx |\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\t0x%016llx\n", |
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iova >> VTD_PAGE_SHIFT, path[5], path[4], |
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path[3], path[2], path[1]); |
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} |
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static void pgtable_walk_level(struct seq_file *m, struct dma_pte *pde, |
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int level, unsigned long start, |
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u64 *path) |
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{ |
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int i; |
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if (level > 5 || level < 1) |
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return; |
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for (i = 0; i < BIT_ULL(VTD_STRIDE_SHIFT); |
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i++, pde++, start += level_to_directory_size(level)) { |
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if (!dma_pte_present(pde)) |
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continue; |
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path[level] = pde->val; |
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if (dma_pte_superpage(pde) || level == 1) |
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dump_page_info(m, start, path); |
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else |
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pgtable_walk_level(m, phys_to_virt(dma_pte_addr(pde)), |
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level - 1, start, path); |
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path[level] = 0; |
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} |
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} |
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static int show_device_domain_translation(struct device *dev, void *data) |
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{ |
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struct dmar_domain *domain = find_domain(dev); |
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struct seq_file *m = data; |
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u64 path[6] = { 0 }; |
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if (!domain) |
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return 0; |
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seq_printf(m, "Device %s with pasid %d @0x%llx\n", |
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dev_name(dev), domain->default_pasid, |
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(u64)virt_to_phys(domain->pgd)); |
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seq_puts(m, "IOVA_PFN\t\tPML5E\t\t\tPML4E\t\t\tPDPE\t\t\tPDE\t\t\tPTE\n"); |
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pgtable_walk_level(m, domain->pgd, domain->agaw + 2, 0, path); |
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seq_putc(m, '\n'); |
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return 0; |
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} |
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static int domain_translation_struct_show(struct seq_file *m, void *unused) |
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{ |
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unsigned long flags; |
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int ret; |
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spin_lock_irqsave(&device_domain_lock, flags); |
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ret = bus_for_each_dev(&pci_bus_type, NULL, m, |
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show_device_domain_translation); |
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spin_unlock_irqrestore(&device_domain_lock, flags); |
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return ret; |
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} |
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DEFINE_SHOW_ATTRIBUTE(domain_translation_struct); |
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static void invalidation_queue_entry_show(struct seq_file *m, |
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struct intel_iommu *iommu) |
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{ |
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int index, shift = qi_shift(iommu); |
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struct qi_desc *desc; |
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int offset; |
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if (ecap_smts(iommu->ecap)) |
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seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tqw2\t\t\tqw3\t\t\tstatus\n"); |
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else |
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seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tstatus\n"); |
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for (index = 0; index < QI_LENGTH; index++) { |
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offset = index << shift; |
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desc = iommu->qi->desc + offset; |
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if (ecap_smts(iommu->ecap)) |
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seq_printf(m, "%5d\t%016llx\t%016llx\t%016llx\t%016llx\t%016x\n", |
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index, desc->qw0, desc->qw1, |
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desc->qw2, desc->qw3, |
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iommu->qi->desc_status[index]); |
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else |
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seq_printf(m, "%5d\t%016llx\t%016llx\t%016x\n", |
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index, desc->qw0, desc->qw1, |
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iommu->qi->desc_status[index]); |
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} |
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} |
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static int invalidation_queue_show(struct seq_file *m, void *unused) |
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{ |
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struct dmar_drhd_unit *drhd; |
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struct intel_iommu *iommu; |
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unsigned long flags; |
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struct q_inval *qi; |
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int shift; |
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rcu_read_lock(); |
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for_each_active_iommu(iommu, drhd) { |
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qi = iommu->qi; |
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shift = qi_shift(iommu); |
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if (!qi || !ecap_qis(iommu->ecap)) |
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continue; |
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seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name); |
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raw_spin_lock_irqsave(&qi->q_lock, flags); |
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seq_printf(m, " Base: 0x%llx\tHead: %lld\tTail: %lld\n", |
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(u64)virt_to_phys(qi->desc), |
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dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift, |
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dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift); |
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invalidation_queue_entry_show(m, iommu); |
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raw_spin_unlock_irqrestore(&qi->q_lock, flags); |
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seq_putc(m, '\n'); |
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} |
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rcu_read_unlock(); |
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return 0; |
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} |
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DEFINE_SHOW_ATTRIBUTE(invalidation_queue); |
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|
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#ifdef CONFIG_IRQ_REMAP |
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static void ir_tbl_remap_entry_show(struct seq_file *m, |
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struct intel_iommu *iommu) |
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{ |
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struct irte *ri_entry; |
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unsigned long flags; |
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int idx; |
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seq_puts(m, " Entry SrcID DstID Vct IRTE_high\t\tIRTE_low\n"); |
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
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for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) { |
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ri_entry = &iommu->ir_table->base[idx]; |
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if (!ri_entry->present || ri_entry->p_pst) |
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continue; |
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seq_printf(m, " %-5d %02x:%02x.%01x %08x %02x %016llx\t%016llx\n", |
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idx, PCI_BUS_NUM(ri_entry->sid), |
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PCI_SLOT(ri_entry->sid), PCI_FUNC(ri_entry->sid), |
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ri_entry->dest_id, ri_entry->vector, |
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ri_entry->high, ri_entry->low); |
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} |
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
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} |
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static void ir_tbl_posted_entry_show(struct seq_file *m, |
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struct intel_iommu *iommu) |
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{ |
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struct irte *pi_entry; |
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unsigned long flags; |
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int idx; |
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seq_puts(m, " Entry SrcID PDA_high PDA_low Vct IRTE_high\t\tIRTE_low\n"); |
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
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for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) { |
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pi_entry = &iommu->ir_table->base[idx]; |
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if (!pi_entry->present || !pi_entry->p_pst) |
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continue; |
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seq_printf(m, " %-5d %02x:%02x.%01x %08x %08x %02x %016llx\t%016llx\n", |
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idx, PCI_BUS_NUM(pi_entry->sid), |
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PCI_SLOT(pi_entry->sid), PCI_FUNC(pi_entry->sid), |
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pi_entry->pda_h, pi_entry->pda_l << 6, |
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pi_entry->vector, pi_entry->high, |
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pi_entry->low); |
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} |
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
|
} |
|
|
|
/* |
|
* For active IOMMUs go through the Interrupt remapping |
|
* table and print valid entries in a table format for |
|
* Remapped and Posted Interrupts. |
|
*/ |
|
static int ir_translation_struct_show(struct seq_file *m, void *unused) |
|
{ |
|
struct dmar_drhd_unit *drhd; |
|
struct intel_iommu *iommu; |
|
u64 irta; |
|
u32 sts; |
|
|
|
rcu_read_lock(); |
|
for_each_active_iommu(iommu, drhd) { |
|
if (!ecap_ir_support(iommu->ecap)) |
|
continue; |
|
|
|
seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n", |
|
iommu->name); |
|
|
|
sts = dmar_readl(iommu->reg + DMAR_GSTS_REG); |
|
if (iommu->ir_table && (sts & DMA_GSTS_IRES)) { |
|
irta = virt_to_phys(iommu->ir_table->base); |
|
seq_printf(m, " IR table address:%llx\n", irta); |
|
ir_tbl_remap_entry_show(m, iommu); |
|
} else { |
|
seq_puts(m, "Interrupt Remapping is not enabled\n"); |
|
} |
|
seq_putc(m, '\n'); |
|
} |
|
|
|
seq_puts(m, "****\n\n"); |
|
|
|
for_each_active_iommu(iommu, drhd) { |
|
if (!cap_pi_support(iommu->cap)) |
|
continue; |
|
|
|
seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n", |
|
iommu->name); |
|
|
|
if (iommu->ir_table) { |
|
irta = virt_to_phys(iommu->ir_table->base); |
|
seq_printf(m, " IR table address:%llx\n", irta); |
|
ir_tbl_posted_entry_show(m, iommu); |
|
} else { |
|
seq_puts(m, "Interrupt Remapping is not enabled\n"); |
|
} |
|
seq_putc(m, '\n'); |
|
} |
|
rcu_read_unlock(); |
|
|
|
return 0; |
|
} |
|
DEFINE_SHOW_ATTRIBUTE(ir_translation_struct); |
|
#endif |
|
|
|
void __init intel_iommu_debugfs_init(void) |
|
{ |
|
struct dentry *intel_iommu_debug = debugfs_create_dir("intel", |
|
iommu_debugfs_dir); |
|
|
|
debugfs_create_file("iommu_regset", 0444, intel_iommu_debug, NULL, |
|
&iommu_regset_fops); |
|
debugfs_create_file("dmar_translation_struct", 0444, intel_iommu_debug, |
|
NULL, &dmar_translation_struct_fops); |
|
debugfs_create_file("domain_translation_struct", 0444, |
|
intel_iommu_debug, NULL, |
|
&domain_translation_struct_fops); |
|
debugfs_create_file("invalidation_queue", 0444, intel_iommu_debug, |
|
NULL, &invalidation_queue_fops); |
|
#ifdef CONFIG_IRQ_REMAP |
|
debugfs_create_file("ir_translation_struct", 0444, intel_iommu_debug, |
|
NULL, &ir_translation_struct_fops); |
|
#endif |
|
}
|
|
|