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927 lines
25 KiB
927 lines
25 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved. |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/completion.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/iio/adc/qcom-vadc-common.h> |
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#include <linux/iio/iio.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel.h> |
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#include <linux/log2.h> |
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#include <linux/math64.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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#include <dt-bindings/iio/qcom,spmi-vadc.h> |
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#define ADC5_USR_REVISION1 0x0 |
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#define ADC5_USR_STATUS1 0x8 |
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#define ADC5_USR_STATUS1_CONV_FAULT BIT(7) |
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#define ADC5_USR_STATUS1_REQ_STS BIT(1) |
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#define ADC5_USR_STATUS1_EOC BIT(0) |
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#define ADC5_USR_STATUS1_REQ_STS_EOC_MASK 0x3 |
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#define ADC5_USR_STATUS2 0x9 |
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#define ADC5_USR_STATUS2_CONV_SEQ_MASK 0x70 |
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#define ADC5_USR_STATUS2_CONV_SEQ_MASK_SHIFT 0x5 |
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#define ADC5_USR_IBAT_MEAS 0xf |
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#define ADC5_USR_IBAT_MEAS_SUPPORTED BIT(0) |
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#define ADC5_USR_DIG_PARAM 0x42 |
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#define ADC5_USR_DIG_PARAM_CAL_VAL BIT(6) |
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#define ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT 6 |
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#define ADC5_USR_DIG_PARAM_CAL_SEL 0x30 |
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#define ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT 4 |
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#define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL 0xc |
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#define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT 2 |
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#define ADC5_USR_FAST_AVG_CTL 0x43 |
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#define ADC5_USR_FAST_AVG_CTL_EN BIT(7) |
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#define ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK 0x7 |
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#define ADC5_USR_CH_SEL_CTL 0x44 |
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#define ADC5_USR_DELAY_CTL 0x45 |
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#define ADC5_USR_HW_SETTLE_DELAY_MASK 0xf |
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#define ADC5_USR_EN_CTL1 0x46 |
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#define ADC5_USR_EN_CTL1_ADC_EN BIT(7) |
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#define ADC5_USR_CONV_REQ 0x47 |
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#define ADC5_USR_CONV_REQ_REQ BIT(7) |
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#define ADC5_USR_DATA0 0x50 |
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#define ADC5_USR_DATA1 0x51 |
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#define ADC5_USR_IBAT_DATA0 0x52 |
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#define ADC5_USR_IBAT_DATA1 0x53 |
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#define ADC_CHANNEL_OFFSET 0x8 |
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#define ADC_CHANNEL_MASK GENMASK(7, 0) |
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/* |
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* Conversion time varies based on the decimation, clock rate, fast average |
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* samples and measurements queued across different VADC peripherals. |
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* Set the timeout to a max of 100ms. |
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*/ |
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#define ADC5_CONV_TIME_MIN_US 263 |
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#define ADC5_CONV_TIME_MAX_US 264 |
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#define ADC5_CONV_TIME_RETRY 400 |
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#define ADC5_CONV_TIMEOUT msecs_to_jiffies(100) |
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/* Digital version >= 5.3 supports hw_settle_2 */ |
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#define ADC5_HW_SETTLE_DIFF_MINOR 3 |
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#define ADC5_HW_SETTLE_DIFF_MAJOR 5 |
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/* For PMIC7 */ |
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#define ADC_APP_SID 0x40 |
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#define ADC_APP_SID_MASK GENMASK(3, 0) |
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#define ADC7_CONV_TIMEOUT msecs_to_jiffies(10) |
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enum adc5_cal_method { |
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ADC5_NO_CAL = 0, |
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ADC5_RATIOMETRIC_CAL, |
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ADC5_ABSOLUTE_CAL |
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}; |
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enum adc5_cal_val { |
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ADC5_TIMER_CAL = 0, |
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ADC5_NEW_CAL |
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}; |
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/** |
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* struct adc5_channel_prop - ADC channel property. |
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* @channel: channel number, refer to the channel list. |
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* @cal_method: calibration method. |
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* @cal_val: calibration value |
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* @decimation: sampling rate supported for the channel. |
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* @sid: slave id of PMIC owning the channel, for PMIC7. |
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* @prescale: channel scaling performed on the input signal. |
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* @hw_settle_time: the time between AMUX being configured and the |
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* start of conversion. |
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* @avg_samples: ability to provide single result from the ADC |
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* that is an average of multiple measurements. |
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* @scale_fn_type: Represents the scaling function to convert voltage |
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* physical units desired by the client for the channel. |
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* @datasheet_name: Channel name used in device tree. |
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*/ |
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struct adc5_channel_prop { |
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unsigned int channel; |
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enum adc5_cal_method cal_method; |
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enum adc5_cal_val cal_val; |
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unsigned int decimation; |
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unsigned int sid; |
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unsigned int prescale; |
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unsigned int hw_settle_time; |
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unsigned int avg_samples; |
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enum vadc_scale_fn_type scale_fn_type; |
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const char *datasheet_name; |
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}; |
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/** |
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* struct adc5_chip - ADC private structure. |
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* @regmap: SPMI ADC5 peripheral register map field. |
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* @dev: SPMI ADC5 device. |
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* @base: base address for the ADC peripheral. |
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* @nchannels: number of ADC channels. |
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* @chan_props: array of ADC channel properties. |
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* @iio_chans: array of IIO channels specification. |
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* @poll_eoc: use polling instead of interrupt. |
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* @complete: ADC result notification after interrupt is received. |
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* @lock: ADC lock for access to the peripheral. |
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* @data: software configuration data. |
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*/ |
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struct adc5_chip { |
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struct regmap *regmap; |
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struct device *dev; |
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u16 base; |
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unsigned int nchannels; |
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struct adc5_channel_prop *chan_props; |
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struct iio_chan_spec *iio_chans; |
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bool poll_eoc; |
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struct completion complete; |
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struct mutex lock; |
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const struct adc5_data *data; |
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}; |
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static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len) |
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{ |
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return regmap_bulk_read(adc->regmap, adc->base + offset, data, len); |
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} |
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static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len) |
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{ |
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return regmap_bulk_write(adc->regmap, adc->base + offset, data, len); |
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} |
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static int adc5_masked_write(struct adc5_chip *adc, u16 offset, u8 mask, u8 val) |
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{ |
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return regmap_update_bits(adc->regmap, adc->base + offset, mask, val); |
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} |
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static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data) |
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{ |
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int ret; |
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u8 rslt_lsb, rslt_msb; |
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ret = adc5_read(adc, ADC5_USR_DATA0, &rslt_lsb, sizeof(rslt_lsb)); |
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if (ret) |
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return ret; |
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ret = adc5_read(adc, ADC5_USR_DATA1, &rslt_msb, sizeof(rslt_lsb)); |
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if (ret) |
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return ret; |
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*data = (rslt_msb << 8) | rslt_lsb; |
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if (*data == ADC5_USR_DATA_CHECK) { |
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dev_err(adc->dev, "Invalid data:0x%x\n", *data); |
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return -EINVAL; |
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} |
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dev_dbg(adc->dev, "voltage raw code:0x%x\n", *data); |
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return 0; |
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} |
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static int adc5_poll_wait_eoc(struct adc5_chip *adc) |
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{ |
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unsigned int count, retry = ADC5_CONV_TIME_RETRY; |
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u8 status1; |
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int ret; |
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for (count = 0; count < retry; count++) { |
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ret = adc5_read(adc, ADC5_USR_STATUS1, &status1, |
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sizeof(status1)); |
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if (ret) |
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return ret; |
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status1 &= ADC5_USR_STATUS1_REQ_STS_EOC_MASK; |
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if (status1 == ADC5_USR_STATUS1_EOC) |
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return 0; |
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usleep_range(ADC5_CONV_TIME_MIN_US, ADC5_CONV_TIME_MAX_US); |
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} |
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return -ETIMEDOUT; |
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} |
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static void adc5_update_dig_param(struct adc5_chip *adc, |
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struct adc5_channel_prop *prop, u8 *data) |
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{ |
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/* Update calibration value */ |
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*data &= ~ADC5_USR_DIG_PARAM_CAL_VAL; |
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*data |= (prop->cal_val << ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT); |
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/* Update calibration select */ |
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*data &= ~ADC5_USR_DIG_PARAM_CAL_SEL; |
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*data |= (prop->cal_method << ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT); |
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/* Update decimation ratio select */ |
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*data &= ~ADC5_USR_DIG_PARAM_DEC_RATIO_SEL; |
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*data |= (prop->decimation << ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT); |
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} |
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static int adc5_configure(struct adc5_chip *adc, |
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struct adc5_channel_prop *prop) |
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{ |
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int ret; |
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u8 buf[6]; |
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/* Read registers 0x42 through 0x46 */ |
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ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf)); |
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if (ret) |
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return ret; |
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/* Digital param selection */ |
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adc5_update_dig_param(adc, prop, &buf[0]); |
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/* Update fast average sample value */ |
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buf[1] &= (u8) ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK; |
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buf[1] |= prop->avg_samples; |
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/* Select ADC channel */ |
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buf[2] = prop->channel; |
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/* Select HW settle delay for channel */ |
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buf[3] &= (u8) ~ADC5_USR_HW_SETTLE_DELAY_MASK; |
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buf[3] |= prop->hw_settle_time; |
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/* Select ADC enable */ |
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buf[4] |= ADC5_USR_EN_CTL1_ADC_EN; |
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/* Select CONV request */ |
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buf[5] |= ADC5_USR_CONV_REQ_REQ; |
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if (!adc->poll_eoc) |
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reinit_completion(&adc->complete); |
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return adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf)); |
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} |
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static int adc7_configure(struct adc5_chip *adc, |
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struct adc5_channel_prop *prop) |
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{ |
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int ret; |
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u8 conv_req = 0, buf[4]; |
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ret = adc5_masked_write(adc, ADC_APP_SID, ADC_APP_SID_MASK, prop->sid); |
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if (ret) |
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return ret; |
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ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf)); |
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if (ret) |
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return ret; |
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/* Digital param selection */ |
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adc5_update_dig_param(adc, prop, &buf[0]); |
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/* Update fast average sample value */ |
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buf[1] &= ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK; |
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buf[1] |= prop->avg_samples; |
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/* Select ADC channel */ |
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buf[2] = prop->channel; |
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/* Select HW settle delay for channel */ |
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buf[3] &= ~ADC5_USR_HW_SETTLE_DELAY_MASK; |
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buf[3] |= prop->hw_settle_time; |
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/* Select CONV request */ |
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conv_req = ADC5_USR_CONV_REQ_REQ; |
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if (!adc->poll_eoc) |
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reinit_completion(&adc->complete); |
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ret = adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf)); |
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if (ret) |
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return ret; |
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return adc5_write(adc, ADC5_USR_CONV_REQ, &conv_req, 1); |
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} |
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static int adc5_do_conversion(struct adc5_chip *adc, |
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struct adc5_channel_prop *prop, |
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struct iio_chan_spec const *chan, |
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u16 *data_volt, u16 *data_cur) |
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{ |
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int ret; |
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mutex_lock(&adc->lock); |
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ret = adc5_configure(adc, prop); |
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if (ret) { |
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dev_err(adc->dev, "ADC configure failed with %d\n", ret); |
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goto unlock; |
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} |
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if (adc->poll_eoc) { |
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ret = adc5_poll_wait_eoc(adc); |
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if (ret) { |
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dev_err(adc->dev, "EOC bit not set\n"); |
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goto unlock; |
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} |
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} else { |
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ret = wait_for_completion_timeout(&adc->complete, |
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ADC5_CONV_TIMEOUT); |
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if (!ret) { |
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dev_dbg(adc->dev, "Did not get completion timeout.\n"); |
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ret = adc5_poll_wait_eoc(adc); |
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if (ret) { |
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dev_err(adc->dev, "EOC bit not set\n"); |
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goto unlock; |
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} |
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} |
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} |
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ret = adc5_read_voltage_data(adc, data_volt); |
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unlock: |
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mutex_unlock(&adc->lock); |
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return ret; |
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} |
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static int adc7_do_conversion(struct adc5_chip *adc, |
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struct adc5_channel_prop *prop, |
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struct iio_chan_spec const *chan, |
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u16 *data_volt, u16 *data_cur) |
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{ |
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int ret; |
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u8 status; |
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mutex_lock(&adc->lock); |
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ret = adc7_configure(adc, prop); |
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if (ret) { |
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dev_err(adc->dev, "ADC configure failed with %d\n", ret); |
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goto unlock; |
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} |
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/* No support for polling mode at present */ |
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wait_for_completion_timeout(&adc->complete, ADC7_CONV_TIMEOUT); |
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ret = adc5_read(adc, ADC5_USR_STATUS1, &status, 1); |
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if (ret) |
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goto unlock; |
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if (status & ADC5_USR_STATUS1_CONV_FAULT) { |
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dev_err(adc->dev, "Unexpected conversion fault\n"); |
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ret = -EIO; |
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goto unlock; |
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} |
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ret = adc5_read_voltage_data(adc, data_volt); |
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unlock: |
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mutex_unlock(&adc->lock); |
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return ret; |
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} |
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typedef int (*adc_do_conversion)(struct adc5_chip *adc, |
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struct adc5_channel_prop *prop, |
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struct iio_chan_spec const *chan, |
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u16 *data_volt, u16 *data_cur); |
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static irqreturn_t adc5_isr(int irq, void *dev_id) |
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{ |
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struct adc5_chip *adc = dev_id; |
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complete(&adc->complete); |
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return IRQ_HANDLED; |
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} |
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static int adc5_of_xlate(struct iio_dev *indio_dev, |
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const struct of_phandle_args *iiospec) |
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{ |
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struct adc5_chip *adc = iio_priv(indio_dev); |
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int i; |
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for (i = 0; i < adc->nchannels; i++) |
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if (adc->chan_props[i].channel == iiospec->args[0]) |
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return i; |
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return -EINVAL; |
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} |
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static int adc7_of_xlate(struct iio_dev *indio_dev, |
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const struct of_phandle_args *iiospec) |
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{ |
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struct adc5_chip *adc = iio_priv(indio_dev); |
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int i, v_channel; |
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for (i = 0; i < adc->nchannels; i++) { |
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v_channel = (adc->chan_props[i].sid << ADC_CHANNEL_OFFSET) | |
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adc->chan_props[i].channel; |
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if (v_channel == iiospec->args[0]) |
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return i; |
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} |
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return -EINVAL; |
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} |
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static int adc_read_raw_common(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, int *val, int *val2, |
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long mask, adc_do_conversion do_conv) |
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{ |
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struct adc5_chip *adc = iio_priv(indio_dev); |
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struct adc5_channel_prop *prop; |
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u16 adc_code_volt, adc_code_cur; |
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int ret; |
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prop = &adc->chan_props[chan->address]; |
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switch (mask) { |
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case IIO_CHAN_INFO_PROCESSED: |
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ret = do_conv(adc, prop, chan, |
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&adc_code_volt, &adc_code_cur); |
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if (ret) |
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return ret; |
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ret = qcom_adc5_hw_scale(prop->scale_fn_type, |
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prop->prescale, |
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adc->data, |
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adc_code_volt, val); |
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if (ret) |
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return ret; |
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return IIO_VAL_INT; |
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default: |
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return -EINVAL; |
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} |
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} |
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static int adc5_read_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, int *val, int *val2, |
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long mask) |
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{ |
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return adc_read_raw_common(indio_dev, chan, val, val2, |
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mask, adc5_do_conversion); |
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} |
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static int adc7_read_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, int *val, int *val2, |
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long mask) |
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{ |
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return adc_read_raw_common(indio_dev, chan, val, val2, |
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mask, adc7_do_conversion); |
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} |
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static const struct iio_info adc5_info = { |
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.read_raw = adc5_read_raw, |
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.of_xlate = adc5_of_xlate, |
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}; |
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static const struct iio_info adc7_info = { |
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.read_raw = adc7_read_raw, |
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.of_xlate = adc7_of_xlate, |
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}; |
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struct adc5_channels { |
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const char *datasheet_name; |
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unsigned int prescale_index; |
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enum iio_chan_type type; |
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long info_mask; |
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enum vadc_scale_fn_type scale_fn_type; |
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}; |
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/* In these definitions, _pre refers to an index into adc5_prescale_ratios. */ |
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#define ADC5_CHAN(_dname, _type, _mask, _pre, _scale) \ |
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{ \ |
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.datasheet_name = _dname, \ |
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.prescale_index = _pre, \ |
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.type = _type, \ |
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.info_mask = _mask, \ |
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.scale_fn_type = _scale, \ |
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}, \ |
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#define ADC5_CHAN_TEMP(_dname, _pre, _scale) \ |
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ADC5_CHAN(_dname, IIO_TEMP, \ |
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BIT(IIO_CHAN_INFO_PROCESSED), \ |
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_pre, _scale) \ |
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#define ADC5_CHAN_VOLT(_dname, _pre, _scale) \ |
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ADC5_CHAN(_dname, IIO_VOLTAGE, \ |
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BIT(IIO_CHAN_INFO_PROCESSED), \ |
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_pre, _scale) \ |
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static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = { |
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[ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0, |
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SCALE_HW_CALIB_DEFAULT) |
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[ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0, |
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SCALE_HW_CALIB_DEFAULT) |
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[ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1, |
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SCALE_HW_CALIB_DEFAULT) |
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[ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1, |
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SCALE_HW_CALIB_DEFAULT) |
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[ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0, |
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SCALE_HW_CALIB_PMIC_THERM) |
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[ADC5_USB_IN_I] = ADC5_CHAN_VOLT("usb_in_i_uv", 0, |
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SCALE_HW_CALIB_DEFAULT) |
|
[ADC5_USB_IN_V_16] = ADC5_CHAN_VOLT("usb_in_v_div_16", 8, |
|
SCALE_HW_CALIB_DEFAULT) |
|
[ADC5_CHG_TEMP] = ADC5_CHAN_TEMP("chg_temp", 0, |
|
SCALE_HW_CALIB_PM5_CHG_TEMP) |
|
/* Charger prescales SBUx and MID_CHG to fit within 1.8V upper unit */ |
|
[ADC5_SBUx] = ADC5_CHAN_VOLT("chg_sbux", 1, |
|
SCALE_HW_CALIB_DEFAULT) |
|
[ADC5_MID_CHG_DIV6] = ADC5_CHAN_VOLT("chg_mid_chg", 3, |
|
SCALE_HW_CALIB_DEFAULT) |
|
[ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm", 0, |
|
SCALE_HW_CALIB_XOTHERM) |
|
[ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0, |
|
SCALE_HW_CALIB_THERM_100K_PULLUP) |
|
[ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0, |
|
SCALE_HW_CALIB_THERM_100K_PULLUP) |
|
[ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0, |
|
SCALE_HW_CALIB_THERM_100K_PULLUP) |
|
[ADC5_AMUX_THM2] = ADC5_CHAN_TEMP("amux_thm2", 0, |
|
SCALE_HW_CALIB_PM5_SMB_TEMP) |
|
}; |
|
|
|
static const struct adc5_channels adc7_chans_pmic[ADC5_MAX_CHANNEL] = { |
|
[ADC7_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0, |
|
SCALE_HW_CALIB_DEFAULT) |
|
[ADC7_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0, |
|
SCALE_HW_CALIB_DEFAULT) |
|
[ADC7_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1, |
|
SCALE_HW_CALIB_DEFAULT) |
|
[ADC7_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 3, |
|
SCALE_HW_CALIB_DEFAULT) |
|
[ADC7_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0, |
|
SCALE_HW_CALIB_PMIC_THERM_PM7) |
|
[ADC7_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0, |
|
SCALE_HW_CALIB_THERM_100K_PU_PM7) |
|
[ADC7_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0, |
|
SCALE_HW_CALIB_THERM_100K_PU_PM7) |
|
[ADC7_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0, |
|
SCALE_HW_CALIB_THERM_100K_PU_PM7) |
|
[ADC7_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0, |
|
SCALE_HW_CALIB_THERM_100K_PU_PM7) |
|
[ADC7_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0, |
|
SCALE_HW_CALIB_THERM_100K_PU_PM7) |
|
[ADC7_AMUX_THM6_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0, |
|
SCALE_HW_CALIB_THERM_100K_PU_PM7) |
|
[ADC7_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_pu2", 0, |
|
SCALE_HW_CALIB_THERM_100K_PU_PM7) |
|
[ADC7_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_pu2", 0, |
|
SCALE_HW_CALIB_THERM_100K_PU_PM7) |
|
[ADC7_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_pu2", 0, |
|
SCALE_HW_CALIB_THERM_100K_PU_PM7) |
|
[ADC7_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_pu2", 0, |
|
SCALE_HW_CALIB_THERM_100K_PU_PM7) |
|
}; |
|
|
|
static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = { |
|
[ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0, |
|
SCALE_HW_CALIB_DEFAULT) |
|
[ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0, |
|
SCALE_HW_CALIB_DEFAULT) |
|
[ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1, |
|
SCALE_HW_CALIB_DEFAULT) |
|
[ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1, |
|
SCALE_HW_CALIB_DEFAULT) |
|
[ADC5_VCOIN] = ADC5_CHAN_VOLT("vcoin", 1, |
|
SCALE_HW_CALIB_DEFAULT) |
|
[ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0, |
|
SCALE_HW_CALIB_PMIC_THERM) |
|
[ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0, |
|
SCALE_HW_CALIB_THERM_100K_PULLUP) |
|
[ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0, |
|
SCALE_HW_CALIB_THERM_100K_PULLUP) |
|
[ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0, |
|
SCALE_HW_CALIB_THERM_100K_PULLUP) |
|
[ADC5_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_100k_pu", 0, |
|
SCALE_HW_CALIB_THERM_100K_PULLUP) |
|
[ADC5_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_100k_pu", 0, |
|
SCALE_HW_CALIB_THERM_100K_PULLUP) |
|
[ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm_100k_pu", 0, |
|
SCALE_HW_CALIB_THERM_100K_PULLUP) |
|
}; |
|
|
|
static int adc5_get_dt_channel_data(struct adc5_chip *adc, |
|
struct adc5_channel_prop *prop, |
|
struct device_node *node, |
|
const struct adc5_data *data) |
|
{ |
|
const char *name = node->name, *channel_name; |
|
u32 chan, value, varr[2]; |
|
u32 sid = 0; |
|
int ret; |
|
struct device *dev = adc->dev; |
|
|
|
ret = of_property_read_u32(node, "reg", &chan); |
|
if (ret) { |
|
dev_err(dev, "invalid channel number %s\n", name); |
|
return ret; |
|
} |
|
|
|
/* Value read from "reg" is virtual channel number */ |
|
|
|
/* virtual channel number = sid << 8 | channel number */ |
|
|
|
if (adc->data->info == &adc7_info) { |
|
sid = chan >> ADC_CHANNEL_OFFSET; |
|
chan = chan & ADC_CHANNEL_MASK; |
|
} |
|
|
|
if (chan > ADC5_PARALLEL_ISENSE_VBAT_IDATA || |
|
!data->adc_chans[chan].datasheet_name) { |
|
dev_err(dev, "%s invalid channel number %d\n", name, chan); |
|
return -EINVAL; |
|
} |
|
|
|
/* the channel has DT description */ |
|
prop->channel = chan; |
|
prop->sid = sid; |
|
|
|
channel_name = of_get_property(node, |
|
"label", NULL) ? : node->name; |
|
if (!channel_name) { |
|
dev_err(dev, "Invalid channel name\n"); |
|
return -EINVAL; |
|
} |
|
prop->datasheet_name = channel_name; |
|
|
|
ret = of_property_read_u32(node, "qcom,decimation", &value); |
|
if (!ret) { |
|
ret = qcom_adc5_decimation_from_dt(value, data->decimation); |
|
if (ret < 0) { |
|
dev_err(dev, "%02x invalid decimation %d\n", |
|
chan, value); |
|
return ret; |
|
} |
|
prop->decimation = ret; |
|
} else { |
|
prop->decimation = ADC5_DECIMATION_DEFAULT; |
|
} |
|
|
|
ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2); |
|
if (!ret) { |
|
ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); |
|
if (ret < 0) { |
|
dev_err(dev, "%02x invalid pre-scaling <%d %d>\n", |
|
chan, varr[0], varr[1]); |
|
return ret; |
|
} |
|
prop->prescale = ret; |
|
} else { |
|
prop->prescale = |
|
adc->data->adc_chans[prop->channel].prescale_index; |
|
} |
|
|
|
ret = of_property_read_u32(node, "qcom,hw-settle-time", &value); |
|
if (!ret) { |
|
u8 dig_version[2]; |
|
|
|
ret = adc5_read(adc, ADC5_USR_REVISION1, dig_version, |
|
sizeof(dig_version)); |
|
if (ret) { |
|
dev_err(dev, "Invalid dig version read %d\n", ret); |
|
return ret; |
|
} |
|
|
|
dev_dbg(dev, "dig_ver:minor:%d, major:%d\n", dig_version[0], |
|
dig_version[1]); |
|
/* Digital controller >= 5.3 have hw_settle_2 option */ |
|
if ((dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR && |
|
dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) || |
|
adc->data->info == &adc7_info) |
|
ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_2); |
|
else |
|
ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1); |
|
|
|
if (ret < 0) { |
|
dev_err(dev, "%02x invalid hw-settle-time %d us\n", |
|
chan, value); |
|
return ret; |
|
} |
|
prop->hw_settle_time = ret; |
|
} else { |
|
prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME; |
|
} |
|
|
|
ret = of_property_read_u32(node, "qcom,avg-samples", &value); |
|
if (!ret) { |
|
ret = qcom_adc5_avg_samples_from_dt(value); |
|
if (ret < 0) { |
|
dev_err(dev, "%02x invalid avg-samples %d\n", |
|
chan, value); |
|
return ret; |
|
} |
|
prop->avg_samples = ret; |
|
} else { |
|
prop->avg_samples = VADC_DEF_AVG_SAMPLES; |
|
} |
|
|
|
if (of_property_read_bool(node, "qcom,ratiometric")) |
|
prop->cal_method = ADC5_RATIOMETRIC_CAL; |
|
else |
|
prop->cal_method = ADC5_ABSOLUTE_CAL; |
|
|
|
/* |
|
* Default to using timer calibration. Using a fresh calibration value |
|
* for every conversion will increase the overall time for a request. |
|
*/ |
|
prop->cal_val = ADC5_TIMER_CAL; |
|
|
|
dev_dbg(dev, "%02x name %s\n", chan, name); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct adc5_data adc5_data_pmic = { |
|
.full_scale_code_volt = 0x70e4, |
|
.full_scale_code_cur = 0x2710, |
|
.adc_chans = adc5_chans_pmic, |
|
.info = &adc5_info, |
|
.decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) |
|
{250, 420, 840}, |
|
.hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) |
|
{15, 100, 200, 300, 400, 500, 600, 700, |
|
800, 900, 1, 2, 4, 6, 8, 10}, |
|
.hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) |
|
{15, 100, 200, 300, 400, 500, 600, 700, |
|
1, 2, 4, 8, 16, 32, 64, 128}, |
|
}; |
|
|
|
static const struct adc5_data adc7_data_pmic = { |
|
.full_scale_code_volt = 0x70e4, |
|
.adc_chans = adc7_chans_pmic, |
|
.info = &adc7_info, |
|
.decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) |
|
{85, 340, 1360}, |
|
.hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) |
|
{15, 100, 200, 300, 400, 500, 600, 700, |
|
1000, 2000, 4000, 8000, 16000, 32000, |
|
64000, 128000}, |
|
}; |
|
|
|
static const struct adc5_data adc5_data_pmic_rev2 = { |
|
.full_scale_code_volt = 0x4000, |
|
.full_scale_code_cur = 0x1800, |
|
.adc_chans = adc5_chans_rev2, |
|
.info = &adc5_info, |
|
.decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) |
|
{256, 512, 1024}, |
|
.hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) |
|
{0, 100, 200, 300, 400, 500, 600, 700, |
|
800, 900, 1, 2, 4, 6, 8, 10}, |
|
.hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) |
|
{15, 100, 200, 300, 400, 500, 600, 700, |
|
1, 2, 4, 8, 16, 32, 64, 128}, |
|
}; |
|
|
|
static const struct of_device_id adc5_match_table[] = { |
|
{ |
|
.compatible = "qcom,spmi-adc5", |
|
.data = &adc5_data_pmic, |
|
}, |
|
{ |
|
.compatible = "qcom,spmi-adc7", |
|
.data = &adc7_data_pmic, |
|
}, |
|
{ |
|
.compatible = "qcom,spmi-adc-rev2", |
|
.data = &adc5_data_pmic_rev2, |
|
}, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, adc5_match_table); |
|
|
|
static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node) |
|
{ |
|
const struct adc5_channels *adc_chan; |
|
struct iio_chan_spec *iio_chan; |
|
struct adc5_channel_prop prop, *chan_props; |
|
struct device_node *child; |
|
unsigned int index = 0; |
|
int ret; |
|
|
|
adc->nchannels = of_get_available_child_count(node); |
|
if (!adc->nchannels) |
|
return -EINVAL; |
|
|
|
adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels, |
|
sizeof(*adc->iio_chans), GFP_KERNEL); |
|
if (!adc->iio_chans) |
|
return -ENOMEM; |
|
|
|
adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels, |
|
sizeof(*adc->chan_props), GFP_KERNEL); |
|
if (!adc->chan_props) |
|
return -ENOMEM; |
|
|
|
chan_props = adc->chan_props; |
|
iio_chan = adc->iio_chans; |
|
adc->data = of_device_get_match_data(adc->dev); |
|
if (!adc->data) |
|
adc->data = &adc5_data_pmic; |
|
|
|
for_each_available_child_of_node(node, child) { |
|
ret = adc5_get_dt_channel_data(adc, &prop, child, adc->data); |
|
if (ret) { |
|
of_node_put(child); |
|
return ret; |
|
} |
|
|
|
prop.scale_fn_type = |
|
adc->data->adc_chans[prop.channel].scale_fn_type; |
|
*chan_props = prop; |
|
adc_chan = &adc->data->adc_chans[prop.channel]; |
|
|
|
iio_chan->channel = prop.channel; |
|
iio_chan->datasheet_name = prop.datasheet_name; |
|
iio_chan->extend_name = prop.datasheet_name; |
|
iio_chan->info_mask_separate = adc_chan->info_mask; |
|
iio_chan->type = adc_chan->type; |
|
iio_chan->address = index; |
|
iio_chan++; |
|
chan_props++; |
|
index++; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int adc5_probe(struct platform_device *pdev) |
|
{ |
|
struct device_node *node = pdev->dev.of_node; |
|
struct device *dev = &pdev->dev; |
|
struct iio_dev *indio_dev; |
|
struct adc5_chip *adc; |
|
struct regmap *regmap; |
|
int ret, irq_eoc; |
|
u32 reg; |
|
|
|
regmap = dev_get_regmap(dev->parent, NULL); |
|
if (!regmap) |
|
return -ENODEV; |
|
|
|
ret = of_property_read_u32(node, "reg", ®); |
|
if (ret < 0) |
|
return ret; |
|
|
|
indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); |
|
if (!indio_dev) |
|
return -ENOMEM; |
|
|
|
adc = iio_priv(indio_dev); |
|
adc->regmap = regmap; |
|
adc->dev = dev; |
|
adc->base = reg; |
|
|
|
init_completion(&adc->complete); |
|
mutex_init(&adc->lock); |
|
|
|
ret = adc5_get_dt_data(adc, node); |
|
if (ret) { |
|
dev_err(dev, "adc get dt data failed\n"); |
|
return ret; |
|
} |
|
|
|
irq_eoc = platform_get_irq(pdev, 0); |
|
if (irq_eoc < 0) { |
|
if (irq_eoc == -EPROBE_DEFER || irq_eoc == -EINVAL) |
|
return irq_eoc; |
|
adc->poll_eoc = true; |
|
} else { |
|
ret = devm_request_irq(dev, irq_eoc, adc5_isr, 0, |
|
"pm-adc5", adc); |
|
if (ret) |
|
return ret; |
|
} |
|
|
|
indio_dev->name = pdev->name; |
|
indio_dev->modes = INDIO_DIRECT_MODE; |
|
indio_dev->info = adc->data->info; |
|
indio_dev->channels = adc->iio_chans; |
|
indio_dev->num_channels = adc->nchannels; |
|
|
|
return devm_iio_device_register(dev, indio_dev); |
|
} |
|
|
|
static struct platform_driver adc5_driver = { |
|
.driver = { |
|
.name = "qcom-spmi-adc5", |
|
.of_match_table = adc5_match_table, |
|
}, |
|
.probe = adc5_probe, |
|
}; |
|
module_platform_driver(adc5_driver); |
|
|
|
MODULE_ALIAS("platform:qcom-spmi-adc5"); |
|
MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 ADC driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|