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427 lines
10 KiB
427 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* mcp3422.c - driver for the Microchip mcp3421/2/3/4/5/6/7/8 chip family |
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* |
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* Copyright (C) 2013, Angelo Compagnucci |
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* Author: Angelo Compagnucci <[email protected]> |
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* |
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* Datasheet: http://ww1.microchip.com/downloads/en/devicedoc/22088b.pdf |
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* https://ww1.microchip.com/downloads/en/DeviceDoc/22226a.pdf |
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* https://ww1.microchip.com/downloads/en/DeviceDoc/22072b.pdf |
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* |
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* This driver exports the value of analog input voltage to sysfs, the |
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* voltage unit is nV. |
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*/ |
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#include <linux/err.h> |
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#include <linux/i2c.h> |
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#include <linux/module.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/delay.h> |
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#include <linux/sysfs.h> |
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#include <asm/unaligned.h> |
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#include <linux/iio/iio.h> |
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#include <linux/iio/sysfs.h> |
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/* Masks */ |
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#define MCP3422_CHANNEL_MASK 0x60 |
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#define MCP3422_PGA_MASK 0x03 |
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#define MCP3422_SRATE_MASK 0x0C |
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#define MCP3422_SRATE_240 0x0 |
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#define MCP3422_SRATE_60 0x1 |
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#define MCP3422_SRATE_15 0x2 |
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#define MCP3422_SRATE_3 0x3 |
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#define MCP3422_PGA_1 0 |
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#define MCP3422_PGA_2 1 |
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#define MCP3422_PGA_4 2 |
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#define MCP3422_PGA_8 3 |
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#define MCP3422_CONT_SAMPLING 0x10 |
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#define MCP3422_CHANNEL(config) (((config) & MCP3422_CHANNEL_MASK) >> 5) |
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#define MCP3422_PGA(config) ((config) & MCP3422_PGA_MASK) |
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#define MCP3422_SAMPLE_RATE(config) (((config) & MCP3422_SRATE_MASK) >> 2) |
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#define MCP3422_CHANNEL_VALUE(value) (((value) << 5) & MCP3422_CHANNEL_MASK) |
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#define MCP3422_PGA_VALUE(value) ((value) & MCP3422_PGA_MASK) |
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#define MCP3422_SAMPLE_RATE_VALUE(value) ((value << 2) & MCP3422_SRATE_MASK) |
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#define MCP3422_CHAN(_index) \ |
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{ \ |
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.type = IIO_VOLTAGE, \ |
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.indexed = 1, \ |
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.channel = _index, \ |
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ |
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| BIT(IIO_CHAN_INFO_SCALE), \ |
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ |
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} |
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static const int mcp3422_scales[4][4] = { |
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{ 1000000, 500000, 250000, 125000 }, |
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{ 250000, 125000, 62500, 31250 }, |
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{ 62500, 31250, 15625, 7812 }, |
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{ 15625, 7812, 3906, 1953 } }; |
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/* Constant msleep times for data acquisitions */ |
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static const int mcp3422_read_times[4] = { |
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[MCP3422_SRATE_240] = 1000 / 240, |
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[MCP3422_SRATE_60] = 1000 / 60, |
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[MCP3422_SRATE_15] = 1000 / 15, |
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[MCP3422_SRATE_3] = 1000 / 3 }; |
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/* sample rates to integer conversion table */ |
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static const int mcp3422_sample_rates[4] = { |
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[MCP3422_SRATE_240] = 240, |
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[MCP3422_SRATE_60] = 60, |
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[MCP3422_SRATE_15] = 15, |
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[MCP3422_SRATE_3] = 3 }; |
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/* sample rates to sign extension table */ |
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static const int mcp3422_sign_extend[4] = { |
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[MCP3422_SRATE_240] = 11, |
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[MCP3422_SRATE_60] = 13, |
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[MCP3422_SRATE_15] = 15, |
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[MCP3422_SRATE_3] = 17 }; |
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/* Client data (each client gets its own) */ |
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struct mcp3422 { |
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struct i2c_client *i2c; |
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u8 id; |
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u8 config; |
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u8 pga[4]; |
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struct mutex lock; |
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}; |
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static int mcp3422_update_config(struct mcp3422 *adc, u8 newconfig) |
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{ |
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int ret; |
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ret = i2c_master_send(adc->i2c, &newconfig, 1); |
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if (ret > 0) { |
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adc->config = newconfig; |
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ret = 0; |
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} |
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return ret; |
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} |
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static int mcp3422_read(struct mcp3422 *adc, int *value, u8 *config) |
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{ |
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int ret = 0; |
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u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config); |
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u8 buf[4] = {0, 0, 0, 0}; |
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u32 temp; |
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if (sample_rate == MCP3422_SRATE_3) { |
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ret = i2c_master_recv(adc->i2c, buf, 4); |
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temp = get_unaligned_be24(&buf[0]); |
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*config = buf[3]; |
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} else { |
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ret = i2c_master_recv(adc->i2c, buf, 3); |
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temp = get_unaligned_be16(&buf[0]); |
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*config = buf[2]; |
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} |
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*value = sign_extend32(temp, mcp3422_sign_extend[sample_rate]); |
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return ret; |
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} |
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static int mcp3422_read_channel(struct mcp3422 *adc, |
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struct iio_chan_spec const *channel, int *value) |
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{ |
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int ret; |
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u8 config; |
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u8 req_channel = channel->channel; |
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mutex_lock(&adc->lock); |
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if (req_channel != MCP3422_CHANNEL(adc->config)) { |
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config = adc->config; |
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config &= ~MCP3422_CHANNEL_MASK; |
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config |= MCP3422_CHANNEL_VALUE(req_channel); |
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config &= ~MCP3422_PGA_MASK; |
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config |= MCP3422_PGA_VALUE(adc->pga[req_channel]); |
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ret = mcp3422_update_config(adc, config); |
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if (ret < 0) { |
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mutex_unlock(&adc->lock); |
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return ret; |
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} |
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msleep(mcp3422_read_times[MCP3422_SAMPLE_RATE(adc->config)]); |
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} |
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ret = mcp3422_read(adc, value, &config); |
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mutex_unlock(&adc->lock); |
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return ret; |
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} |
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static int mcp3422_read_raw(struct iio_dev *iio, |
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struct iio_chan_spec const *channel, int *val1, |
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int *val2, long mask) |
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{ |
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struct mcp3422 *adc = iio_priv(iio); |
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int err; |
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u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config); |
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u8 pga = MCP3422_PGA(adc->config); |
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switch (mask) { |
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case IIO_CHAN_INFO_RAW: |
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err = mcp3422_read_channel(adc, channel, val1); |
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if (err < 0) |
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return -EINVAL; |
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return IIO_VAL_INT; |
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case IIO_CHAN_INFO_SCALE: |
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*val1 = 0; |
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*val2 = mcp3422_scales[sample_rate][pga]; |
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return IIO_VAL_INT_PLUS_NANO; |
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case IIO_CHAN_INFO_SAMP_FREQ: |
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*val1 = mcp3422_sample_rates[MCP3422_SAMPLE_RATE(adc->config)]; |
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return IIO_VAL_INT; |
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default: |
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break; |
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} |
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return -EINVAL; |
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} |
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static int mcp3422_write_raw(struct iio_dev *iio, |
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struct iio_chan_spec const *channel, int val1, |
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int val2, long mask) |
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{ |
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struct mcp3422 *adc = iio_priv(iio); |
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u8 temp; |
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u8 config = adc->config; |
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u8 req_channel = channel->channel; |
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u8 sample_rate = MCP3422_SAMPLE_RATE(config); |
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u8 i; |
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switch (mask) { |
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case IIO_CHAN_INFO_SCALE: |
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if (val1 != 0) |
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return -EINVAL; |
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for (i = 0; i < ARRAY_SIZE(mcp3422_scales[0]); i++) { |
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if (val2 == mcp3422_scales[sample_rate][i]) { |
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adc->pga[req_channel] = i; |
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config &= ~MCP3422_CHANNEL_MASK; |
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config |= MCP3422_CHANNEL_VALUE(req_channel); |
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config &= ~MCP3422_PGA_MASK; |
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config |= MCP3422_PGA_VALUE(adc->pga[req_channel]); |
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return mcp3422_update_config(adc, config); |
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} |
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} |
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return -EINVAL; |
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case IIO_CHAN_INFO_SAMP_FREQ: |
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switch (val1) { |
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case 240: |
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temp = MCP3422_SRATE_240; |
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break; |
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case 60: |
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temp = MCP3422_SRATE_60; |
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break; |
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case 15: |
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temp = MCP3422_SRATE_15; |
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break; |
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case 3: |
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if (adc->id > 4) |
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return -EINVAL; |
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temp = MCP3422_SRATE_3; |
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break; |
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default: |
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return -EINVAL; |
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} |
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config &= ~MCP3422_CHANNEL_MASK; |
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config |= MCP3422_CHANNEL_VALUE(req_channel); |
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config &= ~MCP3422_SRATE_MASK; |
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config |= MCP3422_SAMPLE_RATE_VALUE(temp); |
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return mcp3422_update_config(adc, config); |
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default: |
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break; |
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} |
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return -EINVAL; |
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} |
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static int mcp3422_write_raw_get_fmt(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, long mask) |
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{ |
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switch (mask) { |
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case IIO_CHAN_INFO_SCALE: |
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return IIO_VAL_INT_PLUS_NANO; |
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case IIO_CHAN_INFO_SAMP_FREQ: |
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return IIO_VAL_INT_PLUS_MICRO; |
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default: |
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return -EINVAL; |
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} |
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} |
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static ssize_t mcp3422_show_samp_freqs(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev)); |
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if (adc->id > 4) |
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return sprintf(buf, "240 60 15\n"); |
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return sprintf(buf, "240 60 15 3\n"); |
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} |
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static ssize_t mcp3422_show_scales(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev)); |
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u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config); |
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return sprintf(buf, "0.%09u 0.%09u 0.%09u 0.%09u\n", |
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mcp3422_scales[sample_rate][0], |
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mcp3422_scales[sample_rate][1], |
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mcp3422_scales[sample_rate][2], |
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mcp3422_scales[sample_rate][3]); |
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} |
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static IIO_DEVICE_ATTR(sampling_frequency_available, S_IRUGO, |
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mcp3422_show_samp_freqs, NULL, 0); |
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static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, |
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mcp3422_show_scales, NULL, 0); |
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static struct attribute *mcp3422_attributes[] = { |
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&iio_dev_attr_sampling_frequency_available.dev_attr.attr, |
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&iio_dev_attr_in_voltage_scale_available.dev_attr.attr, |
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NULL, |
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}; |
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static const struct attribute_group mcp3422_attribute_group = { |
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.attrs = mcp3422_attributes, |
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}; |
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static const struct iio_chan_spec mcp3421_channels[] = { |
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MCP3422_CHAN(0), |
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}; |
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static const struct iio_chan_spec mcp3422_channels[] = { |
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MCP3422_CHAN(0), |
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MCP3422_CHAN(1), |
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}; |
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static const struct iio_chan_spec mcp3424_channels[] = { |
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MCP3422_CHAN(0), |
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MCP3422_CHAN(1), |
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MCP3422_CHAN(2), |
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MCP3422_CHAN(3), |
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}; |
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static const struct iio_info mcp3422_info = { |
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.read_raw = mcp3422_read_raw, |
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.write_raw = mcp3422_write_raw, |
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.write_raw_get_fmt = mcp3422_write_raw_get_fmt, |
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.attrs = &mcp3422_attribute_group, |
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}; |
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static int mcp3422_probe(struct i2c_client *client, |
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const struct i2c_device_id *id) |
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{ |
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struct iio_dev *indio_dev; |
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struct mcp3422 *adc; |
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int err; |
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u8 config; |
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if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) |
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return -EOPNOTSUPP; |
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indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*adc)); |
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if (!indio_dev) |
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return -ENOMEM; |
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adc = iio_priv(indio_dev); |
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adc->i2c = client; |
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adc->id = (u8)(id->driver_data); |
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mutex_init(&adc->lock); |
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indio_dev->name = dev_name(&client->dev); |
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indio_dev->modes = INDIO_DIRECT_MODE; |
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indio_dev->info = &mcp3422_info; |
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switch (adc->id) { |
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case 1: |
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case 5: |
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indio_dev->channels = mcp3421_channels; |
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indio_dev->num_channels = ARRAY_SIZE(mcp3421_channels); |
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break; |
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case 2: |
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case 3: |
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case 6: |
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case 7: |
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indio_dev->channels = mcp3422_channels; |
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indio_dev->num_channels = ARRAY_SIZE(mcp3422_channels); |
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break; |
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case 4: |
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case 8: |
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indio_dev->channels = mcp3424_channels; |
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indio_dev->num_channels = ARRAY_SIZE(mcp3424_channels); |
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break; |
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} |
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/* meaningful default configuration */ |
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config = (MCP3422_CONT_SAMPLING |
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| MCP3422_CHANNEL_VALUE(0) |
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| MCP3422_PGA_VALUE(MCP3422_PGA_1) |
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| MCP3422_SAMPLE_RATE_VALUE(MCP3422_SRATE_240)); |
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err = mcp3422_update_config(adc, config); |
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if (err < 0) |
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return err; |
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err = devm_iio_device_register(&client->dev, indio_dev); |
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if (err < 0) |
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return err; |
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i2c_set_clientdata(client, indio_dev); |
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return 0; |
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} |
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static const struct i2c_device_id mcp3422_id[] = { |
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{ "mcp3421", 1 }, |
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{ "mcp3422", 2 }, |
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{ "mcp3423", 3 }, |
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{ "mcp3424", 4 }, |
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{ "mcp3425", 5 }, |
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{ "mcp3426", 6 }, |
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{ "mcp3427", 7 }, |
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{ "mcp3428", 8 }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(i2c, mcp3422_id); |
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static const struct of_device_id mcp3422_of_match[] = { |
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{ .compatible = "mcp3422" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, mcp3422_of_match); |
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static struct i2c_driver mcp3422_driver = { |
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.driver = { |
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.name = "mcp3422", |
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.of_match_table = mcp3422_of_match, |
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}, |
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.probe = mcp3422_probe, |
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.id_table = mcp3422_id, |
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}; |
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module_i2c_driver(mcp3422_driver); |
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MODULE_AUTHOR("Angelo Compagnucci <[email protected]>"); |
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MODULE_DESCRIPTION("Microchip mcp3421/2/3/4/5/6/7/8 driver"); |
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MODULE_LICENSE("GPL v2");
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