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364 lines
9.3 KiB
364 lines
9.3 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* AD7606 SPI ADC driver |
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* |
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* Copyright 2011 Analog Devices Inc. |
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*/ |
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#include <linux/module.h> |
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#include <linux/spi/spi.h> |
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#include <linux/types.h> |
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#include <linux/err.h> |
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#include <linux/iio/iio.h> |
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#include "ad7606.h" |
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#define MAX_SPI_FREQ_HZ 23500000 /* VDRIVE above 4.75 V */ |
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#define AD7616_CONFIGURATION_REGISTER 0x02 |
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#define AD7616_OS_MASK GENMASK(4, 2) |
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#define AD7616_BURST_MODE BIT(6) |
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#define AD7616_SEQEN_MODE BIT(5) |
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#define AD7616_RANGE_CH_A_ADDR_OFF 0x04 |
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#define AD7616_RANGE_CH_B_ADDR_OFF 0x06 |
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/* |
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* Range of channels from a group are stored in 2 registers. |
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* 0, 1, 2, 3 in a register followed by 4, 5, 6, 7 in second register. |
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* For channels from second group(8-15) the order is the same, only with |
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* an offset of 2 for register address. |
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*/ |
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#define AD7616_RANGE_CH_ADDR(ch) ((ch) >> 2) |
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/* The range of the channel is stored in 2 bits */ |
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#define AD7616_RANGE_CH_MSK(ch) (0b11 << (((ch) & 0b11) * 2)) |
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#define AD7616_RANGE_CH_MODE(ch, mode) ((mode) << ((((ch) & 0b11)) * 2)) |
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#define AD7606_CONFIGURATION_REGISTER 0x02 |
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#define AD7606_SINGLE_DOUT 0x00 |
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/* |
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* Range for AD7606B channels are stored in registers starting with address 0x3. |
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* Each register stores range for 2 channels(4 bits per channel). |
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*/ |
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#define AD7606_RANGE_CH_MSK(ch) (GENMASK(3, 0) << (4 * ((ch) & 0x1))) |
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#define AD7606_RANGE_CH_MODE(ch, mode) \ |
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((GENMASK(3, 0) & mode) << (4 * ((ch) & 0x1))) |
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#define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) |
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#define AD7606_OS_MODE 0x08 |
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static const struct iio_chan_spec ad7616_sw_channels[] = { |
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IIO_CHAN_SOFT_TIMESTAMP(16), |
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AD7616_CHANNEL(0), |
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AD7616_CHANNEL(1), |
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AD7616_CHANNEL(2), |
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AD7616_CHANNEL(3), |
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AD7616_CHANNEL(4), |
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AD7616_CHANNEL(5), |
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AD7616_CHANNEL(6), |
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AD7616_CHANNEL(7), |
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AD7616_CHANNEL(8), |
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AD7616_CHANNEL(9), |
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AD7616_CHANNEL(10), |
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AD7616_CHANNEL(11), |
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AD7616_CHANNEL(12), |
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AD7616_CHANNEL(13), |
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AD7616_CHANNEL(14), |
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AD7616_CHANNEL(15), |
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}; |
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static const struct iio_chan_spec ad7606b_sw_channels[] = { |
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IIO_CHAN_SOFT_TIMESTAMP(8), |
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AD7616_CHANNEL(0), |
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AD7616_CHANNEL(1), |
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AD7616_CHANNEL(2), |
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AD7616_CHANNEL(3), |
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AD7616_CHANNEL(4), |
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AD7616_CHANNEL(5), |
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AD7616_CHANNEL(6), |
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AD7616_CHANNEL(7), |
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}; |
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static const unsigned int ad7606B_oversampling_avail[9] = { |
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1, 2, 4, 8, 16, 32, 64, 128, 256 |
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}; |
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static u16 ad7616_spi_rd_wr_cmd(int addr, char isWriteOp) |
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{ |
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/* |
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* The address of register consist of one w/r bit |
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* 6 bits of address followed by one reserved bit. |
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*/ |
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return ((addr & 0x7F) << 1) | ((isWriteOp & 0x1) << 7); |
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} |
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static u16 ad7606B_spi_rd_wr_cmd(int addr, char is_write_op) |
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{ |
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/* |
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* The address of register consists of one bit which |
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* specifies a read command placed in bit 6, followed by |
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* 6 bits of address. |
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*/ |
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return (addr & 0x3F) | (((~is_write_op) & 0x1) << 6); |
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} |
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static int ad7606_spi_read_block(struct device *dev, |
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int count, void *buf) |
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{ |
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struct spi_device *spi = to_spi_device(dev); |
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int i, ret; |
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unsigned short *data = buf; |
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__be16 *bdata = buf; |
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ret = spi_read(spi, buf, count * 2); |
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if (ret < 0) { |
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dev_err(&spi->dev, "SPI read error\n"); |
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return ret; |
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} |
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for (i = 0; i < count; i++) |
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data[i] = be16_to_cpu(bdata[i]); |
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return 0; |
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} |
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static int ad7606_spi_reg_read(struct ad7606_state *st, unsigned int addr) |
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{ |
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struct spi_device *spi = to_spi_device(st->dev); |
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struct spi_transfer t[] = { |
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{ |
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.tx_buf = &st->d16[0], |
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.len = 2, |
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.cs_change = 0, |
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}, { |
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.rx_buf = &st->d16[1], |
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.len = 2, |
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}, |
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}; |
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int ret; |
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st->d16[0] = cpu_to_be16(st->bops->rd_wr_cmd(addr, 0) << 8); |
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ret = spi_sync_transfer(spi, t, ARRAY_SIZE(t)); |
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if (ret < 0) |
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return ret; |
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return be16_to_cpu(st->d16[1]); |
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} |
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static int ad7606_spi_reg_write(struct ad7606_state *st, |
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unsigned int addr, |
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unsigned int val) |
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{ |
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struct spi_device *spi = to_spi_device(st->dev); |
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st->d16[0] = cpu_to_be16((st->bops->rd_wr_cmd(addr, 1) << 8) | |
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(val & 0x1FF)); |
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return spi_write(spi, &st->d16[0], sizeof(st->d16[0])); |
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} |
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static int ad7606_spi_write_mask(struct ad7606_state *st, |
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unsigned int addr, |
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unsigned long mask, |
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unsigned int val) |
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{ |
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int readval; |
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readval = st->bops->reg_read(st, addr); |
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if (readval < 0) |
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return readval; |
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readval &= ~mask; |
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readval |= val; |
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return st->bops->reg_write(st, addr, readval); |
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} |
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static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int val) |
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{ |
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struct ad7606_state *st = iio_priv(indio_dev); |
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unsigned int ch_addr, mode, ch_index; |
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/* |
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* Ad7616 has 16 channels divided in group A and group B. |
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* The range of channels from A are stored in registers with address 4 |
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* while channels from B are stored in register with address 6. |
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* The last bit from channels determines if it is from group A or B |
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* because the order of channels in iio is 0A, 0B, 1A, 1B... |
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*/ |
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ch_index = ch >> 1; |
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ch_addr = AD7616_RANGE_CH_ADDR(ch_index); |
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if ((ch & 0x1) == 0) /* channel A */ |
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ch_addr += AD7616_RANGE_CH_A_ADDR_OFF; |
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else /* channel B */ |
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ch_addr += AD7616_RANGE_CH_B_ADDR_OFF; |
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/* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */ |
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mode = AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11)); |
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return st->bops->write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index), |
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mode); |
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} |
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static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val) |
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{ |
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struct ad7606_state *st = iio_priv(indio_dev); |
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return st->bops->write_mask(st, AD7616_CONFIGURATION_REGISTER, |
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AD7616_OS_MASK, val << 2); |
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} |
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static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int val) |
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{ |
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struct ad7606_state *st = iio_priv(indio_dev); |
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return ad7606_spi_write_mask(st, |
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AD7606_RANGE_CH_ADDR(ch), |
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AD7606_RANGE_CH_MSK(ch), |
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AD7606_RANGE_CH_MODE(ch, val)); |
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} |
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static int ad7606_write_os_sw(struct iio_dev *indio_dev, int val) |
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{ |
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struct ad7606_state *st = iio_priv(indio_dev); |
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return ad7606_spi_reg_write(st, AD7606_OS_MODE, val); |
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} |
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static int ad7616_sw_mode_config(struct iio_dev *indio_dev) |
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{ |
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struct ad7606_state *st = iio_priv(indio_dev); |
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/* |
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* Scale can be configured individually for each channel |
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* in software mode. |
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*/ |
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indio_dev->channels = ad7616_sw_channels; |
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st->write_scale = ad7616_write_scale_sw; |
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st->write_os = &ad7616_write_os_sw; |
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/* Activate Burst mode and SEQEN MODE */ |
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return st->bops->write_mask(st, |
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AD7616_CONFIGURATION_REGISTER, |
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AD7616_BURST_MODE | AD7616_SEQEN_MODE, |
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AD7616_BURST_MODE | AD7616_SEQEN_MODE); |
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} |
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static int ad7606B_sw_mode_config(struct iio_dev *indio_dev) |
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{ |
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struct ad7606_state *st = iio_priv(indio_dev); |
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unsigned long os[3] = {1}; |
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/* |
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* Software mode is enabled when all three oversampling |
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* pins are set to high. If oversampling gpios are defined |
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* in the device tree, then they need to be set to high, |
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* otherwise, they must be hardwired to VDD |
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*/ |
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if (st->gpio_os) { |
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gpiod_set_array_value(ARRAY_SIZE(os), |
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st->gpio_os->desc, st->gpio_os->info, os); |
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} |
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/* OS of 128 and 256 are available only in software mode */ |
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st->oversampling_avail = ad7606B_oversampling_avail; |
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st->num_os_ratios = ARRAY_SIZE(ad7606B_oversampling_avail); |
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st->write_scale = ad7606_write_scale_sw; |
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st->write_os = &ad7606_write_os_sw; |
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/* Configure device spi to output on a single channel */ |
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st->bops->reg_write(st, |
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AD7606_CONFIGURATION_REGISTER, |
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AD7606_SINGLE_DOUT); |
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/* |
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* Scale can be configured individually for each channel |
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* in software mode. |
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*/ |
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indio_dev->channels = ad7606b_sw_channels; |
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return 0; |
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} |
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static const struct ad7606_bus_ops ad7606_spi_bops = { |
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.read_block = ad7606_spi_read_block, |
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}; |
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static const struct ad7606_bus_ops ad7616_spi_bops = { |
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.read_block = ad7606_spi_read_block, |
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.reg_read = ad7606_spi_reg_read, |
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.reg_write = ad7606_spi_reg_write, |
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.write_mask = ad7606_spi_write_mask, |
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.rd_wr_cmd = ad7616_spi_rd_wr_cmd, |
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.sw_mode_config = ad7616_sw_mode_config, |
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}; |
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static const struct ad7606_bus_ops ad7606B_spi_bops = { |
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.read_block = ad7606_spi_read_block, |
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.reg_read = ad7606_spi_reg_read, |
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.reg_write = ad7606_spi_reg_write, |
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.write_mask = ad7606_spi_write_mask, |
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.rd_wr_cmd = ad7606B_spi_rd_wr_cmd, |
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.sw_mode_config = ad7606B_sw_mode_config, |
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}; |
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static int ad7606_spi_probe(struct spi_device *spi) |
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{ |
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const struct spi_device_id *id = spi_get_device_id(spi); |
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const struct ad7606_bus_ops *bops; |
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switch (id->driver_data) { |
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case ID_AD7616: |
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bops = &ad7616_spi_bops; |
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break; |
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case ID_AD7606B: |
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bops = &ad7606B_spi_bops; |
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break; |
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default: |
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bops = &ad7606_spi_bops; |
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break; |
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} |
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return ad7606_probe(&spi->dev, spi->irq, NULL, |
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id->name, id->driver_data, |
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bops); |
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} |
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static const struct spi_device_id ad7606_id_table[] = { |
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{ "ad7605-4", ID_AD7605_4 }, |
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{ "ad7606-4", ID_AD7606_4 }, |
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{ "ad7606-6", ID_AD7606_6 }, |
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{ "ad7606-8", ID_AD7606_8 }, |
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{ "ad7606b", ID_AD7606B }, |
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{ "ad7616", ID_AD7616 }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(spi, ad7606_id_table); |
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static const struct of_device_id ad7606_of_match[] = { |
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{ .compatible = "adi,ad7605-4" }, |
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{ .compatible = "adi,ad7606-4" }, |
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{ .compatible = "adi,ad7606-6" }, |
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{ .compatible = "adi,ad7606-8" }, |
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{ .compatible = "adi,ad7606b" }, |
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{ .compatible = "adi,ad7616" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, ad7606_of_match); |
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static struct spi_driver ad7606_driver = { |
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.driver = { |
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.name = "ad7606", |
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.of_match_table = ad7606_of_match, |
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.pm = AD7606_PM_OPS, |
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}, |
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.probe = ad7606_spi_probe, |
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.id_table = ad7606_id_table, |
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}; |
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module_spi_driver(ad7606_driver); |
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MODULE_AUTHOR("Michael Hennerich <[email protected]>"); |
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MODULE_DESCRIPTION("Analog Devices AD7606 ADC"); |
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MODULE_LICENSE("GPL v2");
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