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63 lines
1.4 KiB
63 lines
1.4 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) 2016-2018 Xilinx |
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*/ |
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#ifndef __LINUX_CLK_ZYNQMP_H_ |
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#define __LINUX_CLK_ZYNQMP_H_ |
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#include <linux/spinlock.h> |
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#include <linux/firmware/xlnx-zynqmp.h> |
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enum topology_type { |
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TYPE_INVALID, |
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TYPE_MUX, |
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TYPE_PLL, |
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TYPE_FIXEDFACTOR, |
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TYPE_DIV1, |
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TYPE_DIV2, |
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TYPE_GATE, |
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}; |
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/** |
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* struct clock_topology - Clock topology |
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* @type: Type of topology |
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* @flag: Topology flags |
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* @type_flag: Topology type specific flag |
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*/ |
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struct clock_topology { |
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u32 type; |
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u32 flag; |
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u32 type_flag; |
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u8 custom_type_flag; |
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}; |
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struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id, |
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const char * const *parents, |
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u8 num_parents, |
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const struct clock_topology *nodes); |
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struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id, |
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const char * const *parents, |
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u8 num_parents, |
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const struct clock_topology *nodes); |
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struct clk_hw *zynqmp_clk_register_divider(const char *name, |
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u32 clk_id, |
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const char * const *parents, |
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u8 num_parents, |
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const struct clock_topology *nodes); |
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struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, |
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const char * const *parents, |
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u8 num_parents, |
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const struct clock_topology *nodes); |
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struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, |
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u32 clk_id, |
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const char * const *parents, |
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u8 num_parents, |
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const struct clock_topology *nodes); |
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#endif
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