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138 lines
3.3 KiB
138 lines
3.3 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Zynq UltraScale+ MPSoC mux |
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* |
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* Copyright (C) 2016-2018 Xilinx |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/slab.h> |
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#include "clk-zynqmp.h" |
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/* |
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* DOC: basic adjustable multiplexer clock that cannot gate |
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* |
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* Traits of this clock: |
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* prepare - clk_prepare only ensures that parents are prepared |
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* enable - clk_enable only ensures that parents are enabled |
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* rate - rate is only affected by parent switching. No clk_set_rate support |
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* parent - parent is adjustable through clk_set_parent |
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*/ |
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/** |
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* struct zynqmp_clk_mux - multiplexer clock |
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* |
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* @hw: handle between common and hardware-specific interfaces |
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* @flags: hardware-specific flags |
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* @clk_id: Id of clock |
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*/ |
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struct zynqmp_clk_mux { |
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struct clk_hw hw; |
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u8 flags; |
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u32 clk_id; |
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}; |
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#define to_zynqmp_clk_mux(_hw) container_of(_hw, struct zynqmp_clk_mux, hw) |
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/** |
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* zynqmp_clk_mux_get_parent() - Get parent of clock |
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* @hw: handle between common and hardware-specific interfaces |
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* |
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* Return: Parent index |
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*/ |
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static u8 zynqmp_clk_mux_get_parent(struct clk_hw *hw) |
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{ |
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struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw); |
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const char *clk_name = clk_hw_get_name(hw); |
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u32 clk_id = mux->clk_id; |
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u32 val; |
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int ret; |
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ret = zynqmp_pm_clock_getparent(clk_id, &val); |
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if (ret) |
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pr_warn_once("%s() getparent failed for clock: %s, ret = %d\n", |
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__func__, clk_name, ret); |
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return val; |
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} |
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/** |
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* zynqmp_clk_mux_set_parent() - Set parent of clock |
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* @hw: handle between common and hardware-specific interfaces |
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* @index: Parent index |
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* |
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* Return: 0 on success else error+reason |
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*/ |
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static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index) |
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{ |
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struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw); |
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const char *clk_name = clk_hw_get_name(hw); |
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u32 clk_id = mux->clk_id; |
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int ret; |
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ret = zynqmp_pm_clock_setparent(clk_id, index); |
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if (ret) |
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pr_warn_once("%s() set parent failed for clock: %s, ret = %d\n", |
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__func__, clk_name, ret); |
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return ret; |
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} |
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static const struct clk_ops zynqmp_clk_mux_ops = { |
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.get_parent = zynqmp_clk_mux_get_parent, |
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.set_parent = zynqmp_clk_mux_set_parent, |
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.determine_rate = __clk_mux_determine_rate, |
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}; |
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static const struct clk_ops zynqmp_clk_mux_ro_ops = { |
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.get_parent = zynqmp_clk_mux_get_parent, |
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}; |
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/** |
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* zynqmp_clk_register_mux() - Register a mux table with the clock |
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* framework |
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* @name: Name of this clock |
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* @clk_id: Id of this clock |
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* @parents: Name of this clock's parents |
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* @num_parents: Number of parents |
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* @nodes: Clock topology node |
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* |
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* Return: clock hardware of the registered clock mux |
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*/ |
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struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id, |
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const char * const *parents, |
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u8 num_parents, |
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const struct clock_topology *nodes) |
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{ |
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struct zynqmp_clk_mux *mux; |
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struct clk_hw *hw; |
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struct clk_init_data init; |
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int ret; |
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mux = kzalloc(sizeof(*mux), GFP_KERNEL); |
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if (!mux) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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if (nodes->type_flag & CLK_MUX_READ_ONLY) |
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init.ops = &zynqmp_clk_mux_ro_ops; |
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else |
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init.ops = &zynqmp_clk_mux_ops; |
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init.flags = nodes->flag; |
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init.parent_names = parents; |
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init.num_parents = num_parents; |
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mux->flags = nodes->type_flag; |
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mux->hw.init = &init; |
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mux->clk_id = clk_id; |
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hw = &mux->hw; |
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ret = clk_hw_register(NULL, hw); |
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if (ret) { |
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kfree(hw); |
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hw = ERR_PTR(ret); |
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} |
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return hw; |
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}
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