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615 lines
21 KiB
615 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Zynq clock controller |
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* |
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* Copyright (C) 2012 - 2013 Xilinx |
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* |
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* Sören Brinkmann <[email protected]> |
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*/ |
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|
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#include <linux/clk/zynq.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/slab.h> |
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#include <linux/string.h> |
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#include <linux/io.h> |
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static void __iomem *zynq_clkc_base; |
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|
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#define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00) |
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#define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04) |
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#define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08) |
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#define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c) |
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#define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20) |
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#define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24) |
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#define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28) |
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#define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c) |
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#define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40) |
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#define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44) |
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#define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48) |
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#define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c) |
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#define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50) |
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#define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54) |
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#define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58) |
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#define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c) |
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#define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60) |
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#define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64) |
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#define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68) |
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#define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70) |
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#define SLCR_621_TRUE (zynq_clkc_base + 0xc4) |
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#define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204) |
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#define NUM_MIO_PINS 54 |
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#define DBG_CLK_CTRL_CLKACT_TRC BIT(0) |
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#define DBG_CLK_CTRL_CPU_1XCLKACT BIT(1) |
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enum zynq_clk { |
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armpll, ddrpll, iopll, |
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cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x, |
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ddr2x, ddr3x, dci, |
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lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1, |
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sdio0, sdio1, uart0, uart1, spi0, spi1, dma, |
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usb0_aper, usb1_aper, gem0_aper, gem1_aper, |
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sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper, |
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i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, |
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smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; |
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static struct clk *ps_clk; |
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static struct clk *clks[clk_max]; |
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static struct clk_onecell_data clk_data; |
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static DEFINE_SPINLOCK(armpll_lock); |
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static DEFINE_SPINLOCK(ddrpll_lock); |
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static DEFINE_SPINLOCK(iopll_lock); |
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static DEFINE_SPINLOCK(armclk_lock); |
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static DEFINE_SPINLOCK(swdtclk_lock); |
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static DEFINE_SPINLOCK(ddrclk_lock); |
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static DEFINE_SPINLOCK(dciclk_lock); |
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static DEFINE_SPINLOCK(gem0clk_lock); |
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static DEFINE_SPINLOCK(gem1clk_lock); |
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static DEFINE_SPINLOCK(canclk_lock); |
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static DEFINE_SPINLOCK(canmioclk_lock); |
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static DEFINE_SPINLOCK(dbgclk_lock); |
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static DEFINE_SPINLOCK(aperclk_lock); |
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static const char *const armpll_parents[] __initconst = {"armpll_int", |
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"ps_clk"}; |
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static const char *const ddrpll_parents[] __initconst = {"ddrpll_int", |
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"ps_clk"}; |
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static const char *const iopll_parents[] __initconst = {"iopll_int", |
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"ps_clk"}; |
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static const char *gem0_mux_parents[] __initdata = {"gem0_div1", "dummy_name"}; |
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static const char *gem1_mux_parents[] __initdata = {"gem1_div1", "dummy_name"}; |
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static const char *const can0_mio_mux2_parents[] __initconst = {"can0_gate", |
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"can0_mio_mux"}; |
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static const char *const can1_mio_mux2_parents[] __initconst = {"can1_gate", |
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"can1_mio_mux"}; |
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static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div", |
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"dummy_name"}; |
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static const char *const dbgtrc_emio_input_names[] __initconst = { |
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"trace_emio_clk"}; |
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static const char *const gem0_emio_input_names[] __initconst = { |
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"gem0_emio_clk"}; |
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static const char *const gem1_emio_input_names[] __initconst = { |
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"gem1_emio_clk"}; |
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static const char *const swdt_ext_clk_input_names[] __initconst = { |
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"swdt_ext_clk"}; |
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static void __init zynq_clk_register_fclk(enum zynq_clk fclk, |
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const char *clk_name, void __iomem *fclk_ctrl_reg, |
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const char **parents, int enable) |
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{ |
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u32 enable_reg; |
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char *mux_name; |
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char *div0_name; |
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char *div1_name; |
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spinlock_t *fclk_lock; |
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spinlock_t *fclk_gate_lock; |
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void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; |
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fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL); |
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if (!fclk_lock) |
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goto err; |
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fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL); |
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if (!fclk_gate_lock) |
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goto err_fclk_gate_lock; |
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spin_lock_init(fclk_lock); |
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spin_lock_init(fclk_gate_lock); |
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mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); |
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if (!mux_name) |
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goto err_mux_name; |
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div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); |
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if (!div0_name) |
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goto err_div0_name; |
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div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); |
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if (!div1_name) |
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goto err_div1_name; |
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clk_register_mux(NULL, mux_name, parents, 4, |
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CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0, |
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fclk_lock); |
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clk_register_divider(NULL, div0_name, mux_name, |
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0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | |
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CLK_DIVIDER_ALLOW_ZERO, fclk_lock); |
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clk_register_divider(NULL, div1_name, div0_name, |
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CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, |
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
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fclk_lock); |
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clks[fclk] = clk_register_gate(NULL, clk_name, |
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div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, |
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0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); |
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enable_reg = readl(fclk_gate_reg) & 1; |
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if (enable && !enable_reg) { |
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if (clk_prepare_enable(clks[fclk])) |
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pr_warn("%s: FCLK%u enable failed\n", __func__, |
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fclk - fclk0); |
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} |
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kfree(mux_name); |
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kfree(div0_name); |
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kfree(div1_name); |
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return; |
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err_div1_name: |
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kfree(div0_name); |
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err_div0_name: |
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kfree(mux_name); |
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err_mux_name: |
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kfree(fclk_gate_lock); |
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err_fclk_gate_lock: |
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kfree(fclk_lock); |
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err: |
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clks[fclk] = ERR_PTR(-ENOMEM); |
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} |
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static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, |
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enum zynq_clk clk1, const char *clk_name0, |
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const char *clk_name1, void __iomem *clk_ctrl, |
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const char **parents, unsigned int two_gates) |
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{ |
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char *mux_name; |
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char *div_name; |
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spinlock_t *lock; |
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lock = kmalloc(sizeof(*lock), GFP_KERNEL); |
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if (!lock) |
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goto err; |
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spin_lock_init(lock); |
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mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); |
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div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); |
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clk_register_mux(NULL, mux_name, parents, 4, |
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CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock); |
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clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, |
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); |
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clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, |
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CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); |
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if (two_gates) |
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clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, |
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CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); |
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kfree(mux_name); |
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kfree(div_name); |
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return; |
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err: |
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clks[clk0] = ERR_PTR(-ENOMEM); |
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if (two_gates) |
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clks[clk1] = ERR_PTR(-ENOMEM); |
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} |
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static void __init zynq_clk_setup(struct device_node *np) |
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{ |
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int i; |
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u32 tmp; |
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int ret; |
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char *clk_name; |
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unsigned int fclk_enable = 0; |
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const char *clk_output_name[clk_max]; |
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const char *cpu_parents[4]; |
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const char *periph_parents[4]; |
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const char *swdt_ext_clk_mux_parents[2]; |
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const char *can_mio_mux_parents[NUM_MIO_PINS]; |
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const char *dummy_nm = "dummy_name"; |
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pr_info("Zynq clock init\n"); |
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/* get clock output names from DT */ |
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for (i = 0; i < clk_max; i++) { |
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if (of_property_read_string_index(np, "clock-output-names", |
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i, &clk_output_name[i])) { |
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pr_err("%s: clock output name not in DT\n", __func__); |
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BUG(); |
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} |
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} |
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cpu_parents[0] = clk_output_name[armpll]; |
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cpu_parents[1] = clk_output_name[armpll]; |
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cpu_parents[2] = clk_output_name[ddrpll]; |
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cpu_parents[3] = clk_output_name[iopll]; |
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periph_parents[0] = clk_output_name[iopll]; |
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periph_parents[1] = clk_output_name[iopll]; |
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periph_parents[2] = clk_output_name[armpll]; |
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periph_parents[3] = clk_output_name[ddrpll]; |
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of_property_read_u32(np, "fclk-enable", &fclk_enable); |
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/* ps_clk */ |
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ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); |
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if (ret) { |
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pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); |
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tmp = 33333333; |
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} |
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ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp); |
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/* PLLs */ |
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clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, |
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SLCR_PLL_STATUS, 0, &armpll_lock); |
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clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], |
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armpll_parents, 2, CLK_SET_RATE_NO_REPARENT, |
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SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock); |
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clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, |
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SLCR_PLL_STATUS, 1, &ddrpll_lock); |
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clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], |
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ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT, |
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SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock); |
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clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, |
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SLCR_PLL_STATUS, 2, &iopll_lock); |
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clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], |
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iopll_parents, 2, CLK_SET_RATE_NO_REPARENT, |
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SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock); |
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/* CPU clocks */ |
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tmp = readl(SLCR_621_TRUE) & 1; |
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clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, |
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CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0, |
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&armclk_lock); |
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clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, |
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SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | |
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CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); |
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clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], |
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"cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
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SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); |
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clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, |
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1, 2); |
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clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x], |
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"cpu_3or2x_div", CLK_IGNORE_UNUSED, |
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SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock); |
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clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1, |
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2 + tmp); |
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clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], |
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"cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, |
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26, 0, &armclk_lock); |
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clk_prepare_enable(clks[cpu_2x]); |
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clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, |
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4 + 2 * tmp); |
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clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x], |
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"cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27, |
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0, &armclk_lock); |
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/* Timers */ |
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swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x]; |
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for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) { |
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int idx = of_property_match_string(np, "clock-names", |
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swdt_ext_clk_input_names[i]); |
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if (idx >= 0) |
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swdt_ext_clk_mux_parents[i + 1] = |
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of_clk_get_parent_name(np, idx); |
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else |
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swdt_ext_clk_mux_parents[i + 1] = dummy_nm; |
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} |
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clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], |
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swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT | |
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CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0, |
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&swdtclk_lock); |
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/* DDR clocks */ |
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clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, |
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SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | |
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CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); |
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clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], |
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"ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); |
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clk_prepare_enable(clks[ddr2x]); |
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clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, |
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SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | |
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CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); |
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clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], |
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"ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); |
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clk_prepare_enable(clks[ddr3x]); |
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clk_register_divider(NULL, "dci_div0", "ddrpll", 0, |
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SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | |
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CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); |
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clk_register_divider(NULL, "dci_div1", "dci_div0", |
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CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, |
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
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&dciclk_lock); |
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clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", |
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CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, |
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&dciclk_lock); |
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clk_prepare_enable(clks[dci]); |
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/* Peripheral clocks */ |
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for (i = fclk0; i <= fclk3; i++) { |
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int enable = !!(fclk_enable & BIT(i - fclk0)); |
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zynq_clk_register_fclk(i, clk_output_name[i], |
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SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), |
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periph_parents, enable); |
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} |
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zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, |
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SLCR_LQSPI_CLK_CTRL, periph_parents, 0); |
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zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL, |
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SLCR_SMC_CLK_CTRL, periph_parents, 0); |
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zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL, |
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SLCR_PCAP_CLK_CTRL, periph_parents, 0); |
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zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], |
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clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, |
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periph_parents, 1); |
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zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0], |
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clk_output_name[uart1], SLCR_UART_CLK_CTRL, |
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periph_parents, 1); |
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zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0], |
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clk_output_name[spi1], SLCR_SPI_CLK_CTRL, |
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periph_parents, 1); |
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for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) { |
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int idx = of_property_match_string(np, "clock-names", |
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gem0_emio_input_names[i]); |
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if (idx >= 0) |
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gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, |
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idx); |
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} |
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clk_register_mux(NULL, "gem0_mux", periph_parents, 4, |
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CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0, |
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&gem0clk_lock); |
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clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, |
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SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | |
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CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); |
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clk_register_divider(NULL, "gem0_div1", "gem0_div0", |
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CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, |
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
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&gem0clk_lock); |
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clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, |
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
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SLCR_GEM0_CLK_CTRL, 6, 1, 0, |
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&gem0clk_lock); |
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clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], |
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"gem0_emio_mux", CLK_SET_RATE_PARENT, |
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SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); |
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|
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for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) { |
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int idx = of_property_match_string(np, "clock-names", |
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gem1_emio_input_names[i]); |
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if (idx >= 0) |
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gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, |
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idx); |
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} |
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clk_register_mux(NULL, "gem1_mux", periph_parents, 4, |
|
CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0, |
|
&gem1clk_lock); |
|
clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, |
|
SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | |
|
CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); |
|
clk_register_divider(NULL, "gem1_div1", "gem1_div0", |
|
CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, |
|
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
|
&gem1clk_lock); |
|
clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, |
|
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
|
SLCR_GEM1_CLK_CTRL, 6, 1, 0, |
|
&gem1clk_lock); |
|
clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], |
|
"gem1_emio_mux", CLK_SET_RATE_PARENT, |
|
SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); |
|
|
|
tmp = strlen("mio_clk_00x"); |
|
clk_name = kmalloc(tmp, GFP_KERNEL); |
|
for (i = 0; i < NUM_MIO_PINS; i++) { |
|
int idx; |
|
|
|
snprintf(clk_name, tmp, "mio_clk_%2.2d", i); |
|
idx = of_property_match_string(np, "clock-names", clk_name); |
|
if (idx >= 0) |
|
can_mio_mux_parents[i] = of_clk_get_parent_name(np, |
|
idx); |
|
else |
|
can_mio_mux_parents[i] = dummy_nm; |
|
} |
|
kfree(clk_name); |
|
clk_register_mux(NULL, "can_mux", periph_parents, 4, |
|
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0, |
|
&canclk_lock); |
|
clk_register_divider(NULL, "can_div0", "can_mux", 0, |
|
SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | |
|
CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); |
|
clk_register_divider(NULL, "can_div1", "can_div0", |
|
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6, |
|
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
|
&canclk_lock); |
|
clk_register_gate(NULL, "can0_gate", "can_div1", |
|
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0, |
|
&canclk_lock); |
|
clk_register_gate(NULL, "can1_gate", "can_div1", |
|
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, |
|
&canclk_lock); |
|
clk_register_mux(NULL, "can0_mio_mux", |
|
can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | |
|
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, |
|
&canmioclk_lock); |
|
clk_register_mux(NULL, "can1_mio_mux", |
|
can_mio_mux_parents, 54, CLK_SET_RATE_PARENT | |
|
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6, |
|
0, &canmioclk_lock); |
|
clks[can0] = clk_register_mux(NULL, clk_output_name[can0], |
|
can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | |
|
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, |
|
&canmioclk_lock); |
|
clks[can1] = clk_register_mux(NULL, clk_output_name[can1], |
|
can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT | |
|
CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1, |
|
0, &canmioclk_lock); |
|
|
|
for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { |
|
int idx = of_property_match_string(np, "clock-names", |
|
dbgtrc_emio_input_names[i]); |
|
if (idx >= 0) |
|
dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, |
|
idx); |
|
} |
|
clk_register_mux(NULL, "dbg_mux", periph_parents, 4, |
|
CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0, |
|
&dbgclk_lock); |
|
clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, |
|
SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | |
|
CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); |
|
clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, |
|
CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0, |
|
&dbgclk_lock); |
|
clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], |
|
"dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, |
|
0, 0, &dbgclk_lock); |
|
clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb], |
|
clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, |
|
&dbgclk_lock); |
|
|
|
/* leave debug clocks in the state the bootloader set them up to */ |
|
tmp = readl(SLCR_DBG_CLK_CTRL); |
|
if (tmp & DBG_CLK_CTRL_CLKACT_TRC) |
|
if (clk_prepare_enable(clks[dbg_trc])) |
|
pr_warn("%s: trace clk enable failed\n", __func__); |
|
if (tmp & DBG_CLK_CTRL_CPU_1XCLKACT) |
|
if (clk_prepare_enable(clks[dbg_apb])) |
|
pr_warn("%s: debug APB clk enable failed\n", __func__); |
|
|
|
/* One gated clock for all APER clocks. */ |
|
clks[dma] = clk_register_gate(NULL, clk_output_name[dma], |
|
clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, |
|
&aperclk_lock); |
|
clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0, |
|
&aperclk_lock); |
|
clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0, |
|
&aperclk_lock); |
|
clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0, |
|
&aperclk_lock); |
|
clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0, |
|
&aperclk_lock); |
|
clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0, |
|
&aperclk_lock); |
|
clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0, |
|
&aperclk_lock); |
|
clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0, |
|
&aperclk_lock); |
|
clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0, |
|
&aperclk_lock); |
|
clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0, |
|
&aperclk_lock); |
|
clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0, |
|
&aperclk_lock); |
|
clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0, |
|
&aperclk_lock); |
|
clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0, |
|
&aperclk_lock); |
|
clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0, |
|
&aperclk_lock); |
|
clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0, |
|
&aperclk_lock); |
|
clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0, |
|
&aperclk_lock); |
|
clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0, |
|
&aperclk_lock); |
|
clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper], |
|
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0, |
|
&aperclk_lock); |
|
|
|
for (i = 0; i < ARRAY_SIZE(clks); i++) { |
|
if (IS_ERR(clks[i])) { |
|
pr_err("Zynq clk %d: register failed with %ld\n", |
|
i, PTR_ERR(clks[i])); |
|
BUG(); |
|
} |
|
} |
|
|
|
clk_data.clks = clks; |
|
clk_data.clk_num = ARRAY_SIZE(clks); |
|
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
|
} |
|
|
|
CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); |
|
|
|
void __init zynq_clock_init(void) |
|
{ |
|
struct device_node *np; |
|
struct device_node *slcr; |
|
struct resource res; |
|
|
|
np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc"); |
|
if (!np) { |
|
pr_err("%s: clkc node not found\n", __func__); |
|
goto np_err; |
|
} |
|
|
|
if (of_address_to_resource(np, 0, &res)) { |
|
pr_err("%pOFn: failed to get resource\n", np); |
|
goto np_err; |
|
} |
|
|
|
slcr = of_get_parent(np); |
|
|
|
if (slcr->data) { |
|
zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; |
|
} else { |
|
pr_err("%pOFn: Unable to get I/O memory\n", np); |
|
of_node_put(slcr); |
|
goto np_err; |
|
} |
|
|
|
pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base); |
|
|
|
of_node_put(slcr); |
|
of_node_put(np); |
|
|
|
return; |
|
|
|
np_err: |
|
of_node_put(np); |
|
BUG(); |
|
}
|
|
|