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156 lines
3.6 KiB
156 lines
3.6 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2020 Intel Corporation. |
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* Zhu YiXin <[email protected]> |
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* Rahul Tanwar <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/iopoll.h> |
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#include <linux/of.h> |
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#include "clk-cgu.h" |
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#define to_lgm_clk_pll(_hw) container_of(_hw, struct lgm_clk_pll, hw) |
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#define PLL_REF_DIV(x) ((x) + 0x08) |
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/* |
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* Calculate formula: |
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* rate = (prate * mult + (prate * frac) / frac_div) / div |
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*/ |
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static unsigned long |
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lgm_pll_calc_rate(unsigned long prate, unsigned int mult, |
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unsigned int div, unsigned int frac, unsigned int frac_div) |
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{ |
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u64 crate, frate, rate64; |
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rate64 = prate; |
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crate = rate64 * mult; |
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frate = rate64 * frac; |
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do_div(frate, frac_div); |
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crate += frate; |
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do_div(crate, div); |
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return crate; |
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} |
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static unsigned long lgm_pll_recalc_rate(struct clk_hw *hw, unsigned long prate) |
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{ |
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struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); |
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unsigned int div, mult, frac; |
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unsigned long flags; |
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spin_lock_irqsave(&pll->lock, flags); |
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mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); |
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div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); |
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frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); |
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spin_unlock_irqrestore(&pll->lock, flags); |
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if (pll->type == TYPE_LJPLL) |
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div *= 4; |
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return lgm_pll_calc_rate(prate, mult, div, frac, BIT(24)); |
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} |
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static int lgm_pll_is_enabled(struct clk_hw *hw) |
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{ |
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struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); |
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unsigned long flags; |
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unsigned int ret; |
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spin_lock_irqsave(&pll->lock, flags); |
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ret = lgm_get_clk_val(pll->membase, pll->reg, 0, 1); |
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spin_unlock_irqrestore(&pll->lock, flags); |
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return ret; |
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} |
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static int lgm_pll_enable(struct clk_hw *hw) |
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{ |
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struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); |
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unsigned long flags; |
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u32 val; |
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int ret; |
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spin_lock_irqsave(&pll->lock, flags); |
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lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 1); |
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ret = readl_poll_timeout_atomic(pll->membase + pll->reg, |
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val, (val & 0x1), 1, 100); |
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spin_unlock_irqrestore(&pll->lock, flags); |
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return ret; |
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} |
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static void lgm_pll_disable(struct clk_hw *hw) |
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{ |
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struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); |
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unsigned long flags; |
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spin_lock_irqsave(&pll->lock, flags); |
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lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 0); |
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spin_unlock_irqrestore(&pll->lock, flags); |
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} |
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static const struct clk_ops lgm_pll_ops = { |
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.recalc_rate = lgm_pll_recalc_rate, |
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.is_enabled = lgm_pll_is_enabled, |
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.enable = lgm_pll_enable, |
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.disable = lgm_pll_disable, |
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}; |
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static struct clk_hw * |
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lgm_clk_register_pll(struct lgm_clk_provider *ctx, |
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const struct lgm_pll_clk_data *list) |
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{ |
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struct clk_init_data init = {}; |
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struct lgm_clk_pll *pll; |
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struct device *dev = ctx->dev; |
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struct clk_hw *hw; |
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int ret; |
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init.ops = &lgm_pll_ops; |
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init.name = list->name; |
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init.flags = list->flags; |
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init.parent_data = list->parent_data; |
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init.num_parents = list->num_parents; |
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pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); |
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if (!pll) |
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return ERR_PTR(-ENOMEM); |
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pll->membase = ctx->membase; |
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pll->lock = ctx->lock; |
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pll->reg = list->reg; |
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pll->flags = list->flags; |
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pll->type = list->type; |
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pll->hw.init = &init; |
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hw = &pll->hw; |
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ret = devm_clk_hw_register(dev, hw); |
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if (ret) |
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return ERR_PTR(ret); |
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return hw; |
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} |
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int lgm_clk_register_plls(struct lgm_clk_provider *ctx, |
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const struct lgm_pll_clk_data *list, |
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unsigned int nr_clk) |
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{ |
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struct clk_hw *hw; |
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int i; |
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for (i = 0; i < nr_clk; i++, list++) { |
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hw = lgm_clk_register_pll(ctx, list); |
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if (IS_ERR(hw)) { |
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dev_err(ctx->dev, "failed to register pll: %s\n", |
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list->name); |
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return PTR_ERR(hw); |
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} |
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ctx->clk_data.hws[list->id] = hw; |
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} |
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return 0; |
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}
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