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754 lines
18 KiB
754 lines
18 KiB
/* |
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* OMAP clkctrl clock support |
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* |
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* Copyright (C) 2017 Texas Instruments, Inc. |
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* |
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* Tero Kristo <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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|
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#include <linux/clk-provider.h> |
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#include <linux/slab.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/clk/ti.h> |
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#include <linux/delay.h> |
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#include <linux/timekeeping.h> |
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#include "clock.h" |
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#define NO_IDLEST 0 |
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#define OMAP4_MODULEMODE_MASK 0x3 |
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#define MODULEMODE_HWCTRL 0x1 |
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#define MODULEMODE_SWCTRL 0x2 |
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#define OMAP4_IDLEST_MASK (0x3 << 16) |
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#define OMAP4_IDLEST_SHIFT 16 |
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#define OMAP4_STBYST_MASK BIT(18) |
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#define OMAP4_STBYST_SHIFT 18 |
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#define CLKCTRL_IDLEST_FUNCTIONAL 0x0 |
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#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 |
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#define CLKCTRL_IDLEST_DISABLED 0x3 |
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|
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/* These timeouts are in us */ |
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#define OMAP4_MAX_MODULE_READY_TIME 2000 |
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#define OMAP4_MAX_MODULE_DISABLE_TIME 5000 |
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static bool _early_timeout = true; |
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struct omap_clkctrl_provider { |
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void __iomem *base; |
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struct list_head clocks; |
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char *clkdm_name; |
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}; |
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struct omap_clkctrl_clk { |
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struct clk_hw *clk; |
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u16 reg_offset; |
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int bit_offset; |
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struct list_head node; |
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}; |
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union omap4_timeout { |
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u32 cycles; |
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ktime_t start; |
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}; |
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static const struct omap_clkctrl_data default_clkctrl_data[] __initconst = { |
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{ 0 }, |
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}; |
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static u32 _omap4_idlest(u32 val) |
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{ |
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val &= OMAP4_IDLEST_MASK; |
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val >>= OMAP4_IDLEST_SHIFT; |
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return val; |
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} |
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static bool _omap4_is_idle(u32 val) |
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{ |
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val = _omap4_idlest(val); |
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return val == CLKCTRL_IDLEST_DISABLED; |
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} |
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static bool _omap4_is_ready(u32 val) |
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{ |
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val = _omap4_idlest(val); |
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return val == CLKCTRL_IDLEST_FUNCTIONAL || |
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val == CLKCTRL_IDLEST_INTERFACE_IDLE; |
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} |
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static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout) |
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{ |
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/* |
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* There are two special cases where ktime_to_ns() can't be |
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* used to track the timeouts. First one is during early boot |
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* when the timers haven't been initialized yet. The second |
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* one is during suspend-resume cycle while timekeeping is |
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* being suspended / resumed. Clocksource for the system |
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* can be from a timer that requires pm_runtime access, which |
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* will eventually bring us here with timekeeping_suspended, |
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* during both suspend entry and resume paths. This happens |
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* at least on am43xx platform. Account for flakeyness |
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* with udelay() by multiplying the timeout value by 2. |
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*/ |
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if (unlikely(_early_timeout || timekeeping_suspended)) { |
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if (time->cycles++ < timeout) { |
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udelay(1 * 2); |
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return false; |
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} |
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} else { |
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if (!ktime_to_ns(time->start)) { |
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time->start = ktime_get(); |
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return false; |
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} |
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if (ktime_us_delta(ktime_get(), time->start) < timeout) { |
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cpu_relax(); |
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return false; |
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} |
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} |
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return true; |
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} |
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static int __init _omap4_disable_early_timeout(void) |
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{ |
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_early_timeout = false; |
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return 0; |
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} |
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arch_initcall(_omap4_disable_early_timeout); |
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static int _omap4_clkctrl_clk_enable(struct clk_hw *hw) |
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{ |
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struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
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u32 val; |
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int ret; |
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union omap4_timeout timeout = { 0 }; |
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if (clk->clkdm) { |
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ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); |
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if (ret) { |
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WARN(1, |
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"%s: could not enable %s's clockdomain %s: %d\n", |
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__func__, clk_hw_get_name(hw), |
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clk->clkdm_name, ret); |
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return ret; |
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} |
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} |
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if (!clk->enable_bit) |
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return 0; |
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val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); |
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val &= ~OMAP4_MODULEMODE_MASK; |
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val |= clk->enable_bit; |
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ti_clk_ll_ops->clk_writel(val, &clk->enable_reg); |
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if (test_bit(NO_IDLEST, &clk->flags)) |
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return 0; |
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/* Wait until module is enabled */ |
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while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { |
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if (_omap4_is_timeout(&timeout, OMAP4_MAX_MODULE_READY_TIME)) { |
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pr_err("%s: failed to enable\n", clk_hw_get_name(hw)); |
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return -EBUSY; |
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} |
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} |
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return 0; |
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} |
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static void _omap4_clkctrl_clk_disable(struct clk_hw *hw) |
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{ |
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struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
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u32 val; |
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union omap4_timeout timeout = { 0 }; |
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if (!clk->enable_bit) |
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goto exit; |
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val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); |
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val &= ~OMAP4_MODULEMODE_MASK; |
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ti_clk_ll_ops->clk_writel(val, &clk->enable_reg); |
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if (test_bit(NO_IDLEST, &clk->flags)) |
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goto exit; |
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/* Wait until module is disabled */ |
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while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { |
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if (_omap4_is_timeout(&timeout, |
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OMAP4_MAX_MODULE_DISABLE_TIME)) { |
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pr_err("%s: failed to disable\n", clk_hw_get_name(hw)); |
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break; |
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} |
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} |
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exit: |
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if (clk->clkdm) |
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ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); |
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} |
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static int _omap4_clkctrl_clk_is_enabled(struct clk_hw *hw) |
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{ |
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struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
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u32 val; |
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val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); |
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if (val & clk->enable_bit) |
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return 1; |
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return 0; |
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} |
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static const struct clk_ops omap4_clkctrl_clk_ops = { |
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.enable = _omap4_clkctrl_clk_enable, |
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.disable = _omap4_clkctrl_clk_disable, |
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.is_enabled = _omap4_clkctrl_clk_is_enabled, |
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.init = omap2_init_clk_clkdm, |
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}; |
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static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec, |
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void *data) |
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{ |
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struct omap_clkctrl_provider *provider = data; |
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struct omap_clkctrl_clk *entry; |
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bool found = false; |
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if (clkspec->args_count != 2) |
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return ERR_PTR(-EINVAL); |
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pr_debug("%s: looking for %x:%x\n", __func__, |
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clkspec->args[0], clkspec->args[1]); |
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list_for_each_entry(entry, &provider->clocks, node) { |
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if (entry->reg_offset == clkspec->args[0] && |
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entry->bit_offset == clkspec->args[1]) { |
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found = true; |
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break; |
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} |
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} |
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if (!found) |
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return ERR_PTR(-EINVAL); |
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return entry->clk; |
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} |
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/* Get clkctrl clock base name based on clkctrl_name or dts node */ |
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static const char * __init clkctrl_get_clock_name(struct device_node *np, |
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const char *clkctrl_name, |
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int offset, int index, |
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bool legacy_naming) |
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{ |
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char *clock_name; |
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/* l4per-clkctrl:1234:0 style naming based on clkctrl_name */ |
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if (clkctrl_name && !legacy_naming) { |
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clock_name = kasprintf(GFP_KERNEL, "%s-clkctrl:%04x:%d", |
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clkctrl_name, offset, index); |
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strreplace(clock_name, '_', '-'); |
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return clock_name; |
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} |
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/* l4per:1234:0 old style naming based on clkctrl_name */ |
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if (clkctrl_name) |
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return kasprintf(GFP_KERNEL, "%s_cm:clk:%04x:%d", |
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clkctrl_name, offset, index); |
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/* l4per_cm:1234:0 old style naming based on parent node name */ |
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if (legacy_naming) |
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return kasprintf(GFP_KERNEL, "%pOFn:clk:%04x:%d", |
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np->parent, offset, index); |
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/* l4per-clkctrl:1234:0 style naming based on node name */ |
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return kasprintf(GFP_KERNEL, "%pOFn:%04x:%d", np, offset, index); |
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} |
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static int __init |
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_ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider, |
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struct device_node *node, struct clk_hw *clk_hw, |
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u16 offset, u8 bit, const char * const *parents, |
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int num_parents, const struct clk_ops *ops, |
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const char *clkctrl_name) |
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{ |
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struct clk_init_data init = { NULL }; |
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struct clk *clk; |
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struct omap_clkctrl_clk *clkctrl_clk; |
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int ret = 0; |
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init.name = clkctrl_get_clock_name(node, clkctrl_name, offset, bit, |
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ti_clk_get_features()->flags & |
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TI_CLK_CLKCTRL_COMPAT); |
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clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL); |
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if (!init.name || !clkctrl_clk) { |
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ret = -ENOMEM; |
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goto cleanup; |
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} |
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clk_hw->init = &init; |
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init.parent_names = parents; |
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init.num_parents = num_parents; |
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init.ops = ops; |
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init.flags = 0; |
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clk = ti_clk_register(NULL, clk_hw, init.name); |
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if (IS_ERR_OR_NULL(clk)) { |
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ret = -EINVAL; |
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goto cleanup; |
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} |
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clkctrl_clk->reg_offset = offset; |
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clkctrl_clk->bit_offset = bit; |
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clkctrl_clk->clk = clk_hw; |
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list_add(&clkctrl_clk->node, &provider->clocks); |
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return 0; |
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cleanup: |
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kfree(init.name); |
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kfree(clkctrl_clk); |
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return ret; |
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} |
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static void __init |
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_ti_clkctrl_setup_gate(struct omap_clkctrl_provider *provider, |
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struct device_node *node, u16 offset, |
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const struct omap_clkctrl_bit_data *data, |
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void __iomem *reg, const char *clkctrl_name) |
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{ |
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struct clk_hw_omap *clk_hw; |
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clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); |
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if (!clk_hw) |
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return; |
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clk_hw->enable_bit = data->bit; |
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clk_hw->enable_reg.ptr = reg; |
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if (_ti_clkctrl_clk_register(provider, node, &clk_hw->hw, offset, |
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data->bit, data->parents, 1, |
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&omap_gate_clk_ops, clkctrl_name)) |
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kfree(clk_hw); |
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} |
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static void __init |
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_ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider, |
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struct device_node *node, u16 offset, |
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const struct omap_clkctrl_bit_data *data, |
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void __iomem *reg, const char *clkctrl_name) |
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{ |
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struct clk_omap_mux *mux; |
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int num_parents = 0; |
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const char * const *pname; |
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mux = kzalloc(sizeof(*mux), GFP_KERNEL); |
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if (!mux) |
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return; |
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pname = data->parents; |
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while (*pname) { |
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num_parents++; |
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pname++; |
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} |
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mux->mask = num_parents; |
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if (!(mux->flags & CLK_MUX_INDEX_ONE)) |
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mux->mask--; |
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mux->mask = (1 << fls(mux->mask)) - 1; |
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mux->shift = data->bit; |
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mux->reg.ptr = reg; |
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if (_ti_clkctrl_clk_register(provider, node, &mux->hw, offset, |
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data->bit, data->parents, num_parents, |
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&ti_clk_mux_ops, clkctrl_name)) |
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kfree(mux); |
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} |
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static void __init |
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_ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider, |
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struct device_node *node, u16 offset, |
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const struct omap_clkctrl_bit_data *data, |
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void __iomem *reg, const char *clkctrl_name) |
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{ |
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struct clk_omap_divider *div; |
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const struct omap_clkctrl_div_data *div_data = data->data; |
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u8 div_flags = 0; |
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div = kzalloc(sizeof(*div), GFP_KERNEL); |
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if (!div) |
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return; |
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div->reg.ptr = reg; |
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div->shift = data->bit; |
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div->flags = div_data->flags; |
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if (div->flags & CLK_DIVIDER_POWER_OF_TWO) |
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div_flags |= CLKF_INDEX_POWER_OF_TWO; |
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if (ti_clk_parse_divider_data((int *)div_data->dividers, 0, |
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div_data->max_div, div_flags, |
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div)) { |
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pr_err("%s: Data parsing for %pOF:%04x:%d failed\n", __func__, |
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node, offset, data->bit); |
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kfree(div); |
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return; |
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} |
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if (_ti_clkctrl_clk_register(provider, node, &div->hw, offset, |
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data->bit, data->parents, 1, |
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&ti_clk_divider_ops, clkctrl_name)) |
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kfree(div); |
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} |
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static void __init |
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_ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider, |
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struct device_node *node, |
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const struct omap_clkctrl_reg_data *data, |
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void __iomem *reg, const char *clkctrl_name) |
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{ |
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const struct omap_clkctrl_bit_data *bits = data->bit_data; |
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if (!bits) |
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return; |
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while (bits->bit) { |
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switch (bits->type) { |
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case TI_CLK_GATE: |
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_ti_clkctrl_setup_gate(provider, node, data->offset, |
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bits, reg, clkctrl_name); |
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break; |
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case TI_CLK_DIVIDER: |
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_ti_clkctrl_setup_div(provider, node, data->offset, |
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bits, reg, clkctrl_name); |
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break; |
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case TI_CLK_MUX: |
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_ti_clkctrl_setup_mux(provider, node, data->offset, |
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bits, reg, clkctrl_name); |
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break; |
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default: |
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pr_err("%s: bad subclk type: %d\n", __func__, |
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bits->type); |
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return; |
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} |
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bits++; |
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} |
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} |
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static void __init _clkctrl_add_provider(void *data, |
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struct device_node *np) |
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{ |
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of_clk_add_hw_provider(np, _ti_omap4_clkctrl_xlate, data); |
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} |
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/* Get clock name based on compatible string for clkctrl */ |
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static char * __init clkctrl_get_name(struct device_node *np) |
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{ |
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struct property *prop; |
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const int prefix_len = 11; |
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const char *compat; |
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char *name; |
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of_property_for_each_string(np, "compatible", prop, compat) { |
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if (!strncmp("ti,clkctrl-", compat, prefix_len)) { |
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/* Two letter minimum name length for l3, l4 etc */ |
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if (strnlen(compat + prefix_len, 16) < 2) |
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continue; |
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name = kasprintf(GFP_KERNEL, "%s", compat + prefix_len); |
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if (!name) |
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continue; |
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strreplace(name, '-', '_'); |
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|
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return name; |
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} |
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} |
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return NULL; |
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} |
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static void __init _ti_omap4_clkctrl_setup(struct device_node *node) |
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{ |
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struct omap_clkctrl_provider *provider; |
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const struct omap_clkctrl_data *data = default_clkctrl_data; |
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const struct omap_clkctrl_reg_data *reg_data; |
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struct clk_init_data init = { NULL }; |
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struct clk_hw_omap *hw; |
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struct clk *clk; |
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struct omap_clkctrl_clk *clkctrl_clk = NULL; |
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const __be32 *addrp; |
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bool legacy_naming; |
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char *clkctrl_name; |
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u32 addr; |
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int ret; |
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char *c; |
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u16 soc_mask = 0; |
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|
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if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) && |
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of_node_name_eq(node, "clk")) |
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ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT; |
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|
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addrp = of_get_address(node, 0, NULL, NULL); |
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addr = (u32)of_translate_address(node, addrp); |
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|
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#ifdef CONFIG_ARCH_OMAP4 |
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if (of_machine_is_compatible("ti,omap4")) |
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data = omap4_clkctrl_data; |
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#endif |
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#ifdef CONFIG_SOC_OMAP5 |
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if (of_machine_is_compatible("ti,omap5")) |
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data = omap5_clkctrl_data; |
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#endif |
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#ifdef CONFIG_SOC_DRA7XX |
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if (of_machine_is_compatible("ti,dra7")) { |
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if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) |
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data = dra7_clkctrl_compat_data; |
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else |
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data = dra7_clkctrl_data; |
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} |
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|
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if (of_machine_is_compatible("ti,dra72")) |
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soc_mask = CLKF_SOC_DRA72; |
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if (of_machine_is_compatible("ti,dra74")) |
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soc_mask = CLKF_SOC_DRA74; |
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if (of_machine_is_compatible("ti,dra76")) |
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soc_mask = CLKF_SOC_DRA76; |
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#endif |
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#ifdef CONFIG_SOC_AM33XX |
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if (of_machine_is_compatible("ti,am33xx")) { |
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if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) |
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data = am3_clkctrl_compat_data; |
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else |
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data = am3_clkctrl_data; |
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} |
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#endif |
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#ifdef CONFIG_SOC_AM43XX |
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if (of_machine_is_compatible("ti,am4372")) { |
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if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) |
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data = am4_clkctrl_compat_data; |
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else |
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data = am4_clkctrl_data; |
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} |
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|
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if (of_machine_is_compatible("ti,am438x")) { |
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if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) |
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data = am438x_clkctrl_compat_data; |
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else |
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data = am438x_clkctrl_data; |
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} |
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#endif |
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#ifdef CONFIG_SOC_TI81XX |
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if (of_machine_is_compatible("ti,dm814")) |
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data = dm814_clkctrl_data; |
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|
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if (of_machine_is_compatible("ti,dm816")) |
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data = dm816_clkctrl_data; |
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#endif |
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|
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if (ti_clk_get_features()->flags & TI_CLK_DEVICE_TYPE_GP) |
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soc_mask |= CLKF_SOC_NONSEC; |
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|
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while (data->addr) { |
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if (addr == data->addr) |
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break; |
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|
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data++; |
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} |
|
|
|
if (!data->addr) { |
|
pr_err("%pOF not found from clkctrl data.\n", node); |
|
return; |
|
} |
|
|
|
provider = kzalloc(sizeof(*provider), GFP_KERNEL); |
|
if (!provider) |
|
return; |
|
|
|
provider->base = of_iomap(node, 0); |
|
|
|
legacy_naming = ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT; |
|
clkctrl_name = clkctrl_get_name(node); |
|
if (clkctrl_name) { |
|
provider->clkdm_name = kasprintf(GFP_KERNEL, |
|
"%s_clkdm", clkctrl_name); |
|
goto clkdm_found; |
|
} |
|
|
|
/* |
|
* The code below can be removed when all clkctrl nodes use domain |
|
* specific compatible proprerty and standard clock node naming |
|
*/ |
|
if (legacy_naming) { |
|
provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFnxxx", node->parent); |
|
if (!provider->clkdm_name) { |
|
kfree(provider); |
|
return; |
|
} |
|
|
|
/* |
|
* Create default clkdm name, replace _cm from end of parent |
|
* node name with _clkdm |
|
*/ |
|
provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0; |
|
} else { |
|
provider->clkdm_name = kasprintf(GFP_KERNEL, "%pOFn", node); |
|
if (!provider->clkdm_name) { |
|
kfree(provider); |
|
return; |
|
} |
|
|
|
/* |
|
* Create default clkdm name, replace _clkctrl from end of |
|
* node name with _clkdm |
|
*/ |
|
provider->clkdm_name[strlen(provider->clkdm_name) - 7] = 0; |
|
} |
|
|
|
strcat(provider->clkdm_name, "clkdm"); |
|
|
|
/* Replace any dash from the clkdm name with underscore */ |
|
c = provider->clkdm_name; |
|
|
|
while (*c) { |
|
if (*c == '-') |
|
*c = '_'; |
|
c++; |
|
} |
|
clkdm_found: |
|
INIT_LIST_HEAD(&provider->clocks); |
|
|
|
/* Generate clocks */ |
|
reg_data = data->regs; |
|
|
|
while (reg_data->parent) { |
|
if ((reg_data->flags & CLKF_SOC_MASK) && |
|
(reg_data->flags & soc_mask) == 0) { |
|
reg_data++; |
|
continue; |
|
} |
|
|
|
hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
|
if (!hw) |
|
return; |
|
|
|
hw->enable_reg.ptr = provider->base + reg_data->offset; |
|
|
|
_ti_clkctrl_setup_subclks(provider, node, reg_data, |
|
hw->enable_reg.ptr, clkctrl_name); |
|
|
|
if (reg_data->flags & CLKF_SW_SUP) |
|
hw->enable_bit = MODULEMODE_SWCTRL; |
|
if (reg_data->flags & CLKF_HW_SUP) |
|
hw->enable_bit = MODULEMODE_HWCTRL; |
|
if (reg_data->flags & CLKF_NO_IDLEST) |
|
set_bit(NO_IDLEST, &hw->flags); |
|
|
|
if (reg_data->clkdm_name) |
|
hw->clkdm_name = reg_data->clkdm_name; |
|
else |
|
hw->clkdm_name = provider->clkdm_name; |
|
|
|
init.parent_names = ®_data->parent; |
|
init.num_parents = 1; |
|
init.flags = 0; |
|
if (reg_data->flags & CLKF_SET_RATE_PARENT) |
|
init.flags |= CLK_SET_RATE_PARENT; |
|
|
|
init.name = clkctrl_get_clock_name(node, clkctrl_name, |
|
reg_data->offset, 0, |
|
legacy_naming); |
|
if (!init.name) |
|
goto cleanup; |
|
|
|
clkctrl_clk = kzalloc(sizeof(*clkctrl_clk), GFP_KERNEL); |
|
if (!clkctrl_clk) |
|
goto cleanup; |
|
|
|
init.ops = &omap4_clkctrl_clk_ops; |
|
hw->hw.init = &init; |
|
|
|
clk = ti_clk_register_omap_hw(NULL, &hw->hw, init.name); |
|
if (IS_ERR_OR_NULL(clk)) |
|
goto cleanup; |
|
|
|
clkctrl_clk->reg_offset = reg_data->offset; |
|
clkctrl_clk->clk = &hw->hw; |
|
|
|
list_add(&clkctrl_clk->node, &provider->clocks); |
|
|
|
reg_data++; |
|
} |
|
|
|
ret = of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider); |
|
if (ret == -EPROBE_DEFER) |
|
ti_clk_retry_init(node, provider, _clkctrl_add_provider); |
|
|
|
kfree(clkctrl_name); |
|
|
|
return; |
|
|
|
cleanup: |
|
kfree(hw); |
|
kfree(init.name); |
|
kfree(clkctrl_name); |
|
kfree(clkctrl_clk); |
|
} |
|
CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl", |
|
_ti_omap4_clkctrl_setup); |
|
|
|
/** |
|
* ti_clk_is_in_standby - Check if clkctrl clock is in standby or not |
|
* @clk: clock to check standby status for |
|
* |
|
* Finds whether the provided clock is in standby mode or not. Returns |
|
* true if the provided clock is a clkctrl type clock and it is in standby, |
|
* false otherwise. |
|
*/ |
|
bool ti_clk_is_in_standby(struct clk *clk) |
|
{ |
|
struct clk_hw *hw; |
|
struct clk_hw_omap *hwclk; |
|
u32 val; |
|
|
|
hw = __clk_get_hw(clk); |
|
|
|
if (!omap2_clk_is_hw_omap(hw)) |
|
return false; |
|
|
|
hwclk = to_clk_hw_omap(hw); |
|
|
|
val = ti_clk_ll_ops->clk_readl(&hwclk->enable_reg); |
|
|
|
if (val & OMAP4_STBYST_MASK) |
|
return true; |
|
|
|
return false; |
|
} |
|
EXPORT_SYMBOL_GPL(ti_clk_is_in_standby);
|
|
|