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312 lines
7.4 KiB
312 lines
7.4 KiB
/* |
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* DRA7 ATL (Audio Tracking Logic) clock driver |
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* |
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* Copyright (C) 2013 Texas Instruments, Inc. |
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* |
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* Peter Ujfalusi <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#include <linux/init.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/clk/ti.h> |
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#include "clock.h" |
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#define DRA7_ATL_INSTANCES 4 |
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#define DRA7_ATL_PPMR_REG(id) (0x200 + (id * 0x80)) |
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#define DRA7_ATL_BBSR_REG(id) (0x204 + (id * 0x80)) |
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#define DRA7_ATL_ATLCR_REG(id) (0x208 + (id * 0x80)) |
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#define DRA7_ATL_SWEN_REG(id) (0x210 + (id * 0x80)) |
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#define DRA7_ATL_BWSMUX_REG(id) (0x214 + (id * 0x80)) |
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#define DRA7_ATL_AWSMUX_REG(id) (0x218 + (id * 0x80)) |
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#define DRA7_ATL_PCLKMUX_REG(id) (0x21c + (id * 0x80)) |
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#define DRA7_ATL_SWEN BIT(0) |
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#define DRA7_ATL_DIVIDER_MASK (0x1f) |
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#define DRA7_ATL_PCLKMUX BIT(0) |
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struct dra7_atl_clock_info; |
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struct dra7_atl_desc { |
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struct clk *clk; |
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struct clk_hw hw; |
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struct dra7_atl_clock_info *cinfo; |
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int id; |
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bool probed; /* the driver for the IP has been loaded */ |
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bool valid; /* configured */ |
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bool enabled; |
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u32 bws; /* Baseband Word Select Mux */ |
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u32 aws; /* Audio Word Select Mux */ |
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u32 divider; /* Cached divider value */ |
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}; |
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struct dra7_atl_clock_info { |
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struct device *dev; |
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void __iomem *iobase; |
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struct dra7_atl_desc *cdesc; |
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}; |
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#define to_atl_desc(_hw) container_of(_hw, struct dra7_atl_desc, hw) |
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static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg, |
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u32 val) |
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{ |
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__raw_writel(val, cinfo->iobase + reg); |
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} |
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static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg) |
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{ |
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return __raw_readl(cinfo->iobase + reg); |
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} |
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static int atl_clk_enable(struct clk_hw *hw) |
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{ |
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struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
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if (!cdesc->probed) |
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goto out; |
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if (unlikely(!cdesc->valid)) |
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dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n", |
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cdesc->id); |
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pm_runtime_get_sync(cdesc->cinfo->dev); |
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atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id), |
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cdesc->divider - 1); |
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atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN); |
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out: |
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cdesc->enabled = true; |
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return 0; |
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} |
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static void atl_clk_disable(struct clk_hw *hw) |
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{ |
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struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
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if (!cdesc->probed) |
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goto out; |
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atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0); |
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pm_runtime_put_sync(cdesc->cinfo->dev); |
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out: |
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cdesc->enabled = false; |
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} |
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static int atl_clk_is_enabled(struct clk_hw *hw) |
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{ |
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struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
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return cdesc->enabled; |
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} |
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static unsigned long atl_clk_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
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return parent_rate / cdesc->divider; |
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} |
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static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *parent_rate) |
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{ |
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unsigned divider; |
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divider = (*parent_rate + rate / 2) / rate; |
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if (divider > DRA7_ATL_DIVIDER_MASK + 1) |
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divider = DRA7_ATL_DIVIDER_MASK + 1; |
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return *parent_rate / divider; |
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} |
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static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct dra7_atl_desc *cdesc; |
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u32 divider; |
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if (!hw || !rate) |
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return -EINVAL; |
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cdesc = to_atl_desc(hw); |
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divider = ((parent_rate + rate / 2) / rate) - 1; |
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if (divider > DRA7_ATL_DIVIDER_MASK) |
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divider = DRA7_ATL_DIVIDER_MASK; |
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cdesc->divider = divider + 1; |
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return 0; |
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} |
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static const struct clk_ops atl_clk_ops = { |
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.enable = atl_clk_enable, |
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.disable = atl_clk_disable, |
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.is_enabled = atl_clk_is_enabled, |
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.recalc_rate = atl_clk_recalc_rate, |
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.round_rate = atl_clk_round_rate, |
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.set_rate = atl_clk_set_rate, |
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}; |
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static void __init of_dra7_atl_clock_setup(struct device_node *node) |
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{ |
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struct dra7_atl_desc *clk_hw = NULL; |
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struct clk_init_data init = { NULL }; |
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const char **parent_names = NULL; |
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struct clk *clk; |
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clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); |
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if (!clk_hw) { |
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pr_err("%s: could not allocate dra7_atl_desc\n", __func__); |
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return; |
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} |
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clk_hw->hw.init = &init; |
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clk_hw->divider = 1; |
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init.name = node->name; |
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init.ops = &atl_clk_ops; |
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init.flags = CLK_IGNORE_UNUSED; |
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init.num_parents = of_clk_get_parent_count(node); |
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if (init.num_parents != 1) { |
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pr_err("%s: atl clock %pOFn must have 1 parent\n", __func__, |
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node); |
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goto cleanup; |
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} |
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parent_names = kzalloc(sizeof(char *), GFP_KERNEL); |
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if (!parent_names) |
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goto cleanup; |
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parent_names[0] = of_clk_get_parent_name(node, 0); |
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init.parent_names = parent_names; |
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clk = ti_clk_register(NULL, &clk_hw->hw, node->name); |
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if (!IS_ERR(clk)) { |
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of_clk_add_provider(node, of_clk_src_simple_get, clk); |
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kfree(parent_names); |
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return; |
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} |
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cleanup: |
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kfree(parent_names); |
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kfree(clk_hw); |
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} |
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CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup); |
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static int of_dra7_atl_clk_probe(struct platform_device *pdev) |
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{ |
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struct device_node *node = pdev->dev.of_node; |
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struct dra7_atl_clock_info *cinfo; |
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int i; |
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int ret = 0; |
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if (!node) |
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return -ENODEV; |
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cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL); |
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if (!cinfo) |
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return -ENOMEM; |
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cinfo->iobase = of_iomap(node, 0); |
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cinfo->dev = &pdev->dev; |
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pm_runtime_enable(cinfo->dev); |
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pm_runtime_get_sync(cinfo->dev); |
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atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX); |
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for (i = 0; i < DRA7_ATL_INSTANCES; i++) { |
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struct device_node *cfg_node; |
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char prop[5]; |
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struct dra7_atl_desc *cdesc; |
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struct of_phandle_args clkspec; |
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struct clk *clk; |
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int rc; |
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rc = of_parse_phandle_with_args(node, "ti,provided-clocks", |
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NULL, i, &clkspec); |
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if (rc) { |
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pr_err("%s: failed to lookup atl clock %d\n", __func__, |
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i); |
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return -EINVAL; |
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} |
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clk = of_clk_get_from_provider(&clkspec); |
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if (IS_ERR(clk)) { |
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pr_err("%s: failed to get atl clock %d from provider\n", |
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__func__, i); |
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return PTR_ERR(clk); |
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} |
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cdesc = to_atl_desc(__clk_get_hw(clk)); |
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cdesc->cinfo = cinfo; |
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cdesc->id = i; |
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/* Get configuration for the ATL instances */ |
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snprintf(prop, sizeof(prop), "atl%u", i); |
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cfg_node = of_get_child_by_name(node, prop); |
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if (cfg_node) { |
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ret = of_property_read_u32(cfg_node, "bws", |
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&cdesc->bws); |
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ret |= of_property_read_u32(cfg_node, "aws", |
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&cdesc->aws); |
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if (!ret) { |
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cdesc->valid = true; |
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atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i), |
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cdesc->bws); |
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atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i), |
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cdesc->aws); |
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} |
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of_node_put(cfg_node); |
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} |
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cdesc->probed = true; |
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/* |
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* Enable the clock if it has been asked prior to loading the |
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* hw driver |
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*/ |
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if (cdesc->enabled) |
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atl_clk_enable(__clk_get_hw(clk)); |
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} |
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pm_runtime_put_sync(cinfo->dev); |
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return ret; |
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} |
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static const struct of_device_id of_dra7_atl_clk_match_tbl[] = { |
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{ .compatible = "ti,dra7-atl", }, |
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{}, |
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}; |
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static struct platform_driver dra7_atl_clk_driver = { |
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.driver = { |
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.name = "dra7-atl", |
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.suppress_bind_attrs = true, |
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.of_match_table = of_dra7_atl_clk_match_tbl, |
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}, |
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.probe = of_dra7_atl_clk_probe, |
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}; |
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builtin_platform_driver(dra7_atl_clk_driver);
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