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418 lines
9.5 KiB
418 lines
9.5 KiB
/* |
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* OMAP APLL clock support |
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* |
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* Copyright (C) 2013 Texas Instruments, Inc. |
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* |
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* J Keerthy <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/module.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#include <linux/err.h> |
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#include <linux/string.h> |
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#include <linux/log2.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/clk/ti.h> |
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#include <linux/delay.h> |
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#include "clock.h" |
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#define APLL_FORCE_LOCK 0x1 |
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#define APLL_AUTO_IDLE 0x2 |
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#define MAX_APLL_WAIT_TRIES 1000000 |
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#undef pr_fmt |
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#define pr_fmt(fmt) "%s: " fmt, __func__ |
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static int dra7_apll_enable(struct clk_hw *hw) |
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{ |
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struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
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int r = 0, i = 0; |
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struct dpll_data *ad; |
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const char *clk_name; |
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u8 state = 1; |
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u32 v; |
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ad = clk->dpll_data; |
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if (!ad) |
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return -EINVAL; |
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clk_name = clk_hw_get_name(&clk->hw); |
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state <<= __ffs(ad->idlest_mask); |
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/* Check is already locked */ |
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v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); |
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if ((v & ad->idlest_mask) == state) |
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return r; |
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v = ti_clk_ll_ops->clk_readl(&ad->control_reg); |
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v &= ~ad->enable_mask; |
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v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask); |
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ti_clk_ll_ops->clk_writel(v, &ad->control_reg); |
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state <<= __ffs(ad->idlest_mask); |
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while (1) { |
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v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); |
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if ((v & ad->idlest_mask) == state) |
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break; |
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if (i > MAX_APLL_WAIT_TRIES) |
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break; |
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i++; |
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udelay(1); |
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} |
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if (i == MAX_APLL_WAIT_TRIES) { |
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pr_warn("clock: %s failed transition to '%s'\n", |
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clk_name, (state) ? "locked" : "bypassed"); |
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r = -EBUSY; |
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} else |
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pr_debug("clock: %s transition to '%s' in %d loops\n", |
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clk_name, (state) ? "locked" : "bypassed", i); |
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return r; |
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} |
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static void dra7_apll_disable(struct clk_hw *hw) |
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{ |
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struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
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struct dpll_data *ad; |
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u8 state = 1; |
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u32 v; |
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ad = clk->dpll_data; |
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state <<= __ffs(ad->idlest_mask); |
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v = ti_clk_ll_ops->clk_readl(&ad->control_reg); |
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v &= ~ad->enable_mask; |
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v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask); |
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ti_clk_ll_ops->clk_writel(v, &ad->control_reg); |
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} |
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static int dra7_apll_is_enabled(struct clk_hw *hw) |
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{ |
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struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
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struct dpll_data *ad; |
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u32 v; |
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ad = clk->dpll_data; |
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v = ti_clk_ll_ops->clk_readl(&ad->control_reg); |
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v &= ad->enable_mask; |
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v >>= __ffs(ad->enable_mask); |
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return v == APLL_AUTO_IDLE ? 0 : 1; |
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} |
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static u8 dra7_init_apll_parent(struct clk_hw *hw) |
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{ |
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return 0; |
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} |
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static const struct clk_ops apll_ck_ops = { |
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.enable = &dra7_apll_enable, |
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.disable = &dra7_apll_disable, |
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.is_enabled = &dra7_apll_is_enabled, |
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.get_parent = &dra7_init_apll_parent, |
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}; |
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static void __init omap_clk_register_apll(void *user, |
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struct device_node *node) |
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{ |
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struct clk_hw *hw = user; |
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struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); |
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struct dpll_data *ad = clk_hw->dpll_data; |
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struct clk *clk; |
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const struct clk_init_data *init = clk_hw->hw.init; |
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clk = of_clk_get(node, 0); |
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if (IS_ERR(clk)) { |
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pr_debug("clk-ref for %pOFn not ready, retry\n", |
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node); |
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if (!ti_clk_retry_init(node, hw, omap_clk_register_apll)) |
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return; |
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goto cleanup; |
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} |
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ad->clk_ref = __clk_get_hw(clk); |
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clk = of_clk_get(node, 1); |
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if (IS_ERR(clk)) { |
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pr_debug("clk-bypass for %pOFn not ready, retry\n", |
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node); |
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if (!ti_clk_retry_init(node, hw, omap_clk_register_apll)) |
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return; |
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goto cleanup; |
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} |
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ad->clk_bypass = __clk_get_hw(clk); |
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clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); |
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if (!IS_ERR(clk)) { |
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of_clk_add_provider(node, of_clk_src_simple_get, clk); |
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kfree(init->parent_names); |
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kfree(init); |
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return; |
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} |
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cleanup: |
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kfree(clk_hw->dpll_data); |
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kfree(init->parent_names); |
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kfree(init); |
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kfree(clk_hw); |
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} |
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static void __init of_dra7_apll_setup(struct device_node *node) |
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{ |
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struct dpll_data *ad = NULL; |
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struct clk_hw_omap *clk_hw = NULL; |
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struct clk_init_data *init = NULL; |
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const char **parent_names = NULL; |
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int ret; |
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ad = kzalloc(sizeof(*ad), GFP_KERNEL); |
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clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); |
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init = kzalloc(sizeof(*init), GFP_KERNEL); |
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if (!ad || !clk_hw || !init) |
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goto cleanup; |
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clk_hw->dpll_data = ad; |
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clk_hw->hw.init = init; |
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init->name = node->name; |
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init->ops = &apll_ck_ops; |
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init->num_parents = of_clk_get_parent_count(node); |
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if (init->num_parents < 1) { |
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pr_err("dra7 apll %pOFn must have parent(s)\n", node); |
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goto cleanup; |
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} |
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parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL); |
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if (!parent_names) |
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goto cleanup; |
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of_clk_parent_fill(node, parent_names, init->num_parents); |
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init->parent_names = parent_names; |
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ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); |
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ret |= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg); |
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if (ret) |
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goto cleanup; |
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ad->idlest_mask = 0x1; |
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ad->enable_mask = 0x3; |
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omap_clk_register_apll(&clk_hw->hw, node); |
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return; |
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cleanup: |
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kfree(parent_names); |
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kfree(ad); |
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kfree(clk_hw); |
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kfree(init); |
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} |
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CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup); |
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#define OMAP2_EN_APLL_LOCKED 0x3 |
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#define OMAP2_EN_APLL_STOPPED 0x0 |
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static int omap2_apll_is_enabled(struct clk_hw *hw) |
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{ |
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struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
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struct dpll_data *ad = clk->dpll_data; |
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u32 v; |
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v = ti_clk_ll_ops->clk_readl(&ad->control_reg); |
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v &= ad->enable_mask; |
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v >>= __ffs(ad->enable_mask); |
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return v == OMAP2_EN_APLL_LOCKED ? 1 : 0; |
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} |
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static unsigned long omap2_apll_recalc(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
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if (omap2_apll_is_enabled(hw)) |
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return clk->fixed_rate; |
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return 0; |
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} |
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static int omap2_apll_enable(struct clk_hw *hw) |
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{ |
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struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
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struct dpll_data *ad = clk->dpll_data; |
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u32 v; |
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int i = 0; |
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v = ti_clk_ll_ops->clk_readl(&ad->control_reg); |
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v &= ~ad->enable_mask; |
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v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask); |
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ti_clk_ll_ops->clk_writel(v, &ad->control_reg); |
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while (1) { |
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v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); |
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if (v & ad->idlest_mask) |
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break; |
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if (i > MAX_APLL_WAIT_TRIES) |
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break; |
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i++; |
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udelay(1); |
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} |
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if (i == MAX_APLL_WAIT_TRIES) { |
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pr_warn("%s failed to transition to locked\n", |
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clk_hw_get_name(&clk->hw)); |
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return -EBUSY; |
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} |
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return 0; |
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} |
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static void omap2_apll_disable(struct clk_hw *hw) |
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{ |
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struct clk_hw_omap *clk = to_clk_hw_omap(hw); |
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struct dpll_data *ad = clk->dpll_data; |
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u32 v; |
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v = ti_clk_ll_ops->clk_readl(&ad->control_reg); |
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v &= ~ad->enable_mask; |
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v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask); |
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ti_clk_ll_ops->clk_writel(v, &ad->control_reg); |
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} |
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static const struct clk_ops omap2_apll_ops = { |
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.enable = &omap2_apll_enable, |
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.disable = &omap2_apll_disable, |
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.is_enabled = &omap2_apll_is_enabled, |
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.recalc_rate = &omap2_apll_recalc, |
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}; |
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static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val) |
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{ |
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struct dpll_data *ad = clk->dpll_data; |
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u32 v; |
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v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg); |
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v &= ~ad->autoidle_mask; |
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v |= val << __ffs(ad->autoidle_mask); |
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ti_clk_ll_ops->clk_writel(v, &ad->control_reg); |
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} |
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#define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP 0x3 |
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#define OMAP2_APLL_AUTOIDLE_DISABLE 0x0 |
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static void omap2_apll_allow_idle(struct clk_hw_omap *clk) |
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{ |
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omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP); |
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} |
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static void omap2_apll_deny_idle(struct clk_hw_omap *clk) |
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{ |
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omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE); |
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} |
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static const struct clk_hw_omap_ops omap2_apll_hwops = { |
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.allow_idle = &omap2_apll_allow_idle, |
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.deny_idle = &omap2_apll_deny_idle, |
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}; |
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static void __init of_omap2_apll_setup(struct device_node *node) |
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{ |
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struct dpll_data *ad = NULL; |
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struct clk_hw_omap *clk_hw = NULL; |
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struct clk_init_data *init = NULL; |
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struct clk *clk; |
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const char *parent_name; |
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u32 val; |
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int ret; |
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ad = kzalloc(sizeof(*ad), GFP_KERNEL); |
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clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); |
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init = kzalloc(sizeof(*init), GFP_KERNEL); |
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if (!ad || !clk_hw || !init) |
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goto cleanup; |
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clk_hw->dpll_data = ad; |
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clk_hw->hw.init = init; |
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init->ops = &omap2_apll_ops; |
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init->name = node->name; |
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clk_hw->ops = &omap2_apll_hwops; |
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init->num_parents = of_clk_get_parent_count(node); |
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if (init->num_parents != 1) { |
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pr_err("%pOFn must have one parent\n", node); |
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goto cleanup; |
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} |
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parent_name = of_clk_get_parent_name(node, 0); |
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init->parent_names = &parent_name; |
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if (of_property_read_u32(node, "ti,clock-frequency", &val)) { |
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pr_err("%pOFn missing clock-frequency\n", node); |
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goto cleanup; |
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} |
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clk_hw->fixed_rate = val; |
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if (of_property_read_u32(node, "ti,bit-shift", &val)) { |
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pr_err("%pOFn missing bit-shift\n", node); |
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goto cleanup; |
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} |
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clk_hw->enable_bit = val; |
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ad->enable_mask = 0x3 << val; |
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ad->autoidle_mask = 0x3 << val; |
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if (of_property_read_u32(node, "ti,idlest-shift", &val)) { |
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pr_err("%pOFn missing idlest-shift\n", node); |
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goto cleanup; |
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} |
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ad->idlest_mask = 1 << val; |
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ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); |
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ret |= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg); |
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ret |= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg); |
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if (ret) |
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goto cleanup; |
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clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); |
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if (!IS_ERR(clk)) { |
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of_clk_add_provider(node, of_clk_src_simple_get, clk); |
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kfree(init); |
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return; |
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} |
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cleanup: |
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kfree(ad); |
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kfree(clk_hw); |
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kfree(init); |
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} |
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CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock", |
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of_omap2_apll_setup);
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