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1167 lines
27 KiB
1167 lines
27 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2013 Emilio López |
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* |
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* Emilio López <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/clkdev.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/reset-controller.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/log2.h> |
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#include "clk-factors.h" |
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static DEFINE_SPINLOCK(clk_lock); |
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/* Maximum number of parents our clocks have */ |
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#define SUNXI_MAX_PARENTS 5 |
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/* |
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* sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1 |
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* PLL1 rate is calculated as follows |
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* rate = (parent_rate * n * (k + 1) >> p) / (m + 1); |
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* parent_rate is always 24Mhz |
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*/ |
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static void sun4i_get_pll1_factors(struct factors_request *req) |
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{ |
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u8 div; |
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/* Normalize value to a 6M multiple */ |
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div = req->rate / 6000000; |
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req->rate = 6000000 * div; |
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/* m is always zero for pll1 */ |
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req->m = 0; |
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/* k is 1 only on these cases */ |
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if (req->rate >= 768000000 || req->rate == 42000000 || |
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req->rate == 54000000) |
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req->k = 1; |
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else |
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req->k = 0; |
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/* p will be 3 for divs under 10 */ |
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if (div < 10) |
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req->p = 3; |
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/* p will be 2 for divs between 10 - 20 and odd divs under 32 */ |
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else if (div < 20 || (div < 32 && (div & 1))) |
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req->p = 2; |
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/* p will be 1 for even divs under 32, divs under 40 and odd pairs |
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* of divs between 40-62 */ |
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else if (div < 40 || (div < 64 && (div & 2))) |
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req->p = 1; |
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/* any other entries have p = 0 */ |
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else |
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req->p = 0; |
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/* calculate a suitable n based on k and p */ |
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div <<= req->p; |
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div /= (req->k + 1); |
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req->n = div / 4; |
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} |
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/* |
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* sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1 |
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* PLL1 rate is calculated as follows |
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* rate = parent_rate * (n + 1) * (k + 1) / (m + 1); |
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* parent_rate should always be 24MHz |
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*/ |
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static void sun6i_a31_get_pll1_factors(struct factors_request *req) |
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{ |
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/* |
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* We can operate only on MHz, this will make our life easier |
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* later. |
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*/ |
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u32 freq_mhz = req->rate / 1000000; |
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u32 parent_freq_mhz = req->parent_rate / 1000000; |
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/* |
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* Round down the frequency to the closest multiple of either |
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* 6 or 16 |
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*/ |
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u32 round_freq_6 = rounddown(freq_mhz, 6); |
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u32 round_freq_16 = round_down(freq_mhz, 16); |
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if (round_freq_6 > round_freq_16) |
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freq_mhz = round_freq_6; |
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else |
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freq_mhz = round_freq_16; |
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req->rate = freq_mhz * 1000000; |
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/* If the frequency is a multiple of 32 MHz, k is always 3 */ |
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if (!(freq_mhz % 32)) |
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req->k = 3; |
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/* If the frequency is a multiple of 9 MHz, k is always 2 */ |
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else if (!(freq_mhz % 9)) |
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req->k = 2; |
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/* If the frequency is a multiple of 8 MHz, k is always 1 */ |
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else if (!(freq_mhz % 8)) |
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req->k = 1; |
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/* Otherwise, we don't use the k factor */ |
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else |
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req->k = 0; |
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/* |
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* If the frequency is a multiple of 2 but not a multiple of |
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* 3, m is 3. This is the first time we use 6 here, yet we |
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* will use it on several other places. |
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* We use this number because it's the lowest frequency we can |
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* generate (with n = 0, k = 0, m = 3), so every other frequency |
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* somehow relates to this frequency. |
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*/ |
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if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4) |
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req->m = 2; |
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/* |
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* If the frequency is a multiple of 6MHz, but the factor is |
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* odd, m will be 3 |
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*/ |
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else if ((freq_mhz / 6) & 1) |
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req->m = 3; |
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/* Otherwise, we end up with m = 1 */ |
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else |
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req->m = 1; |
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/* Calculate n thanks to the above factors we already got */ |
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req->n = freq_mhz * (req->m + 1) / ((req->k + 1) * parent_freq_mhz) |
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- 1; |
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/* |
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* If n end up being outbound, and that we can still decrease |
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* m, do it. |
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*/ |
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if ((req->n + 1) > 31 && (req->m + 1) > 1) { |
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req->n = (req->n + 1) / 2 - 1; |
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req->m = (req->m + 1) / 2 - 1; |
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} |
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} |
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/* |
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* sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1 |
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* PLL1 rate is calculated as follows |
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* rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1); |
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* parent_rate is always 24Mhz |
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*/ |
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static void sun8i_a23_get_pll1_factors(struct factors_request *req) |
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{ |
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u8 div; |
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/* Normalize value to a 6M multiple */ |
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div = req->rate / 6000000; |
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req->rate = 6000000 * div; |
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/* m is always zero for pll1 */ |
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req->m = 0; |
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/* k is 1 only on these cases */ |
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if (req->rate >= 768000000 || req->rate == 42000000 || |
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req->rate == 54000000) |
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req->k = 1; |
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else |
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req->k = 0; |
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/* p will be 2 for divs under 20 and odd divs under 32 */ |
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if (div < 20 || (div < 32 && (div & 1))) |
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req->p = 2; |
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/* p will be 1 for even divs under 32, divs under 40 and odd pairs |
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* of divs between 40-62 */ |
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else if (div < 40 || (div < 64 && (div & 2))) |
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req->p = 1; |
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/* any other entries have p = 0 */ |
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else |
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req->p = 0; |
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/* calculate a suitable n based on k and p */ |
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div <<= req->p; |
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div /= (req->k + 1); |
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req->n = div / 4 - 1; |
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} |
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/* |
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* sun4i_get_pll5_factors() - calculates n, k factors for PLL5 |
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* PLL5 rate is calculated as follows |
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* rate = parent_rate * n * (k + 1) |
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* parent_rate is always 24Mhz |
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*/ |
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static void sun4i_get_pll5_factors(struct factors_request *req) |
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{ |
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u8 div; |
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/* Normalize value to a parent_rate multiple (24M) */ |
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div = req->rate / req->parent_rate; |
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req->rate = req->parent_rate * div; |
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if (div < 31) |
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req->k = 0; |
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else if (div / 2 < 31) |
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req->k = 1; |
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else if (div / 3 < 31) |
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req->k = 2; |
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else |
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req->k = 3; |
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req->n = DIV_ROUND_UP(div, (req->k + 1)); |
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} |
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/* |
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* sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2 |
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* PLL6x2 rate is calculated as follows |
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* rate = parent_rate * (n + 1) * (k + 1) |
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* parent_rate is always 24Mhz |
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*/ |
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static void sun6i_a31_get_pll6_factors(struct factors_request *req) |
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{ |
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u8 div; |
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/* Normalize value to a parent_rate multiple (24M) */ |
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div = req->rate / req->parent_rate; |
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req->rate = req->parent_rate * div; |
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req->k = div / 32; |
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if (req->k > 3) |
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req->k = 3; |
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req->n = DIV_ROUND_UP(div, (req->k + 1)) - 1; |
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} |
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/* |
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* sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB |
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* AHB rate is calculated as follows |
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* rate = parent_rate >> p |
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*/ |
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static void sun5i_a13_get_ahb_factors(struct factors_request *req) |
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{ |
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u32 div; |
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/* divide only */ |
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if (req->parent_rate < req->rate) |
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req->rate = req->parent_rate; |
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/* |
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* user manual says valid speed is 8k ~ 276M, but tests show it |
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* can work at speeds up to 300M, just after reparenting to pll6 |
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*/ |
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if (req->rate < 8000) |
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req->rate = 8000; |
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if (req->rate > 300000000) |
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req->rate = 300000000; |
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div = order_base_2(DIV_ROUND_UP(req->parent_rate, req->rate)); |
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/* p = 0 ~ 3 */ |
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if (div > 3) |
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div = 3; |
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req->rate = req->parent_rate >> div; |
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req->p = div; |
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} |
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#define SUN6I_AHB1_PARENT_PLL6 3 |
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/* |
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* sun6i_a31_get_ahb_factors() - calculates m, p factors for AHB |
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* AHB rate is calculated as follows |
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* rate = parent_rate >> p |
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* |
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* if parent is pll6, then |
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* parent_rate = pll6 rate / (m + 1) |
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*/ |
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static void sun6i_get_ahb1_factors(struct factors_request *req) |
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{ |
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u8 div, calcp, calcm = 1; |
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/* |
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* clock can only divide, so we will never be able to achieve |
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* frequencies higher than the parent frequency |
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*/ |
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if (req->parent_rate && req->rate > req->parent_rate) |
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req->rate = req->parent_rate; |
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div = DIV_ROUND_UP(req->parent_rate, req->rate); |
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/* calculate pre-divider if parent is pll6 */ |
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if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) { |
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if (div < 4) |
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calcp = 0; |
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else if (div / 2 < 4) |
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calcp = 1; |
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else if (div / 4 < 4) |
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calcp = 2; |
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else |
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calcp = 3; |
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calcm = DIV_ROUND_UP(div, 1 << calcp); |
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} else { |
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calcp = __roundup_pow_of_two(div); |
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calcp = calcp > 3 ? 3 : calcp; |
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} |
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req->rate = (req->parent_rate / calcm) >> calcp; |
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req->p = calcp; |
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req->m = calcm - 1; |
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} |
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/* |
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* sun6i_ahb1_recalc() - calculates AHB clock rate from m, p factors and |
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* parent index |
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*/ |
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static void sun6i_ahb1_recalc(struct factors_request *req) |
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{ |
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req->rate = req->parent_rate; |
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/* apply pre-divider first if parent is pll6 */ |
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if (req->parent_index == SUN6I_AHB1_PARENT_PLL6) |
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req->rate /= req->m + 1; |
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/* clk divider */ |
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req->rate >>= req->p; |
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} |
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/* |
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* sun4i_get_apb1_factors() - calculates m, p factors for APB1 |
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* APB1 rate is calculated as follows |
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* rate = (parent_rate >> p) / (m + 1); |
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*/ |
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static void sun4i_get_apb1_factors(struct factors_request *req) |
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{ |
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u8 calcm, calcp; |
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int div; |
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if (req->parent_rate < req->rate) |
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req->rate = req->parent_rate; |
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div = DIV_ROUND_UP(req->parent_rate, req->rate); |
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/* Invalid rate! */ |
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if (div > 32) |
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return; |
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if (div <= 4) |
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calcp = 0; |
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else if (div <= 8) |
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calcp = 1; |
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else if (div <= 16) |
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calcp = 2; |
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else |
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calcp = 3; |
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calcm = (div >> calcp) - 1; |
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req->rate = (req->parent_rate >> calcp) / (calcm + 1); |
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req->m = calcm; |
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req->p = calcp; |
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} |
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/* |
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* sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B |
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* CLK_OUT rate is calculated as follows |
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* rate = (parent_rate >> p) / (m + 1); |
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*/ |
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static void sun7i_a20_get_out_factors(struct factors_request *req) |
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{ |
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u8 div, calcm, calcp; |
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/* These clocks can only divide, so we will never be able to achieve |
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* frequencies higher than the parent frequency */ |
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if (req->rate > req->parent_rate) |
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req->rate = req->parent_rate; |
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div = DIV_ROUND_UP(req->parent_rate, req->rate); |
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if (div < 32) |
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calcp = 0; |
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else if (div / 2 < 32) |
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calcp = 1; |
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else if (div / 4 < 32) |
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calcp = 2; |
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else |
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calcp = 3; |
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calcm = DIV_ROUND_UP(div, 1 << calcp); |
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req->rate = (req->parent_rate >> calcp) / calcm; |
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req->m = calcm - 1; |
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req->p = calcp; |
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} |
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/* |
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* sunxi_factors_clk_setup() - Setup function for factor clocks |
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*/ |
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static const struct clk_factors_config sun4i_pll1_config = { |
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.nshift = 8, |
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.nwidth = 5, |
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.kshift = 4, |
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.kwidth = 2, |
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.mshift = 0, |
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.mwidth = 2, |
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.pshift = 16, |
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.pwidth = 2, |
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}; |
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static const struct clk_factors_config sun6i_a31_pll1_config = { |
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.nshift = 8, |
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.nwidth = 5, |
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.kshift = 4, |
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.kwidth = 2, |
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.mshift = 0, |
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.mwidth = 2, |
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.n_start = 1, |
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}; |
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static const struct clk_factors_config sun8i_a23_pll1_config = { |
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.nshift = 8, |
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.nwidth = 5, |
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.kshift = 4, |
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.kwidth = 2, |
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.mshift = 0, |
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.mwidth = 2, |
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.pshift = 16, |
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.pwidth = 2, |
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.n_start = 1, |
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}; |
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static const struct clk_factors_config sun4i_pll5_config = { |
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.nshift = 8, |
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.nwidth = 5, |
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.kshift = 4, |
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.kwidth = 2, |
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}; |
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static const struct clk_factors_config sun6i_a31_pll6_config = { |
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.nshift = 8, |
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.nwidth = 5, |
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.kshift = 4, |
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.kwidth = 2, |
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.n_start = 1, |
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}; |
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static const struct clk_factors_config sun5i_a13_ahb_config = { |
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.pshift = 4, |
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.pwidth = 2, |
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}; |
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static const struct clk_factors_config sun6i_ahb1_config = { |
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.mshift = 6, |
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.mwidth = 2, |
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.pshift = 4, |
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.pwidth = 2, |
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}; |
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static const struct clk_factors_config sun4i_apb1_config = { |
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.mshift = 0, |
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.mwidth = 5, |
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.pshift = 16, |
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.pwidth = 2, |
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}; |
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/* user manual says "n" but it's really "p" */ |
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static const struct clk_factors_config sun7i_a20_out_config = { |
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.mshift = 8, |
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.mwidth = 5, |
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.pshift = 20, |
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.pwidth = 2, |
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}; |
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static const struct factors_data sun4i_pll1_data __initconst = { |
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.enable = 31, |
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.table = &sun4i_pll1_config, |
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.getter = sun4i_get_pll1_factors, |
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}; |
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static const struct factors_data sun6i_a31_pll1_data __initconst = { |
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.enable = 31, |
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.table = &sun6i_a31_pll1_config, |
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.getter = sun6i_a31_get_pll1_factors, |
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}; |
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static const struct factors_data sun8i_a23_pll1_data __initconst = { |
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.enable = 31, |
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.table = &sun8i_a23_pll1_config, |
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.getter = sun8i_a23_get_pll1_factors, |
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}; |
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static const struct factors_data sun7i_a20_pll4_data __initconst = { |
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.enable = 31, |
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.table = &sun4i_pll5_config, |
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.getter = sun4i_get_pll5_factors, |
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}; |
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static const struct factors_data sun4i_pll5_data __initconst = { |
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.enable = 31, |
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.table = &sun4i_pll5_config, |
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.getter = sun4i_get_pll5_factors, |
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}; |
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static const struct factors_data sun6i_a31_pll6_data __initconst = { |
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.enable = 31, |
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.table = &sun6i_a31_pll6_config, |
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.getter = sun6i_a31_get_pll6_factors, |
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}; |
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static const struct factors_data sun5i_a13_ahb_data __initconst = { |
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.mux = 6, |
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.muxmask = BIT(1) | BIT(0), |
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.table = &sun5i_a13_ahb_config, |
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.getter = sun5i_a13_get_ahb_factors, |
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}; |
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static const struct factors_data sun6i_ahb1_data __initconst = { |
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.mux = 12, |
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.muxmask = BIT(1) | BIT(0), |
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.table = &sun6i_ahb1_config, |
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.getter = sun6i_get_ahb1_factors, |
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.recalc = sun6i_ahb1_recalc, |
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}; |
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static const struct factors_data sun4i_apb1_data __initconst = { |
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.mux = 24, |
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.muxmask = BIT(1) | BIT(0), |
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.table = &sun4i_apb1_config, |
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.getter = sun4i_get_apb1_factors, |
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}; |
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static const struct factors_data sun7i_a20_out_data __initconst = { |
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.enable = 31, |
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.mux = 24, |
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.muxmask = BIT(1) | BIT(0), |
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.table = &sun7i_a20_out_config, |
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.getter = sun7i_a20_get_out_factors, |
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}; |
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static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, |
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const struct factors_data *data) |
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{ |
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void __iomem *reg; |
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reg = of_iomap(node, 0); |
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if (!reg) { |
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pr_err("Could not get registers for factors-clk: %pOFn\n", |
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node); |
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return NULL; |
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} |
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return sunxi_factors_register(node, data, &clk_lock, reg); |
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} |
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static void __init sun4i_pll1_clk_setup(struct device_node *node) |
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{ |
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sunxi_factors_clk_setup(node, &sun4i_pll1_data); |
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} |
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CLK_OF_DECLARE(sun4i_pll1, "allwinner,sun4i-a10-pll1-clk", |
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sun4i_pll1_clk_setup); |
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static void __init sun6i_pll1_clk_setup(struct device_node *node) |
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{ |
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sunxi_factors_clk_setup(node, &sun6i_a31_pll1_data); |
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} |
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CLK_OF_DECLARE(sun6i_pll1, "allwinner,sun6i-a31-pll1-clk", |
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sun6i_pll1_clk_setup); |
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|
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static void __init sun8i_pll1_clk_setup(struct device_node *node) |
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{ |
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sunxi_factors_clk_setup(node, &sun8i_a23_pll1_data); |
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} |
|
CLK_OF_DECLARE(sun8i_pll1, "allwinner,sun8i-a23-pll1-clk", |
|
sun8i_pll1_clk_setup); |
|
|
|
static void __init sun7i_pll4_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_factors_clk_setup(node, &sun7i_a20_pll4_data); |
|
} |
|
CLK_OF_DECLARE(sun7i_pll4, "allwinner,sun7i-a20-pll4-clk", |
|
sun7i_pll4_clk_setup); |
|
|
|
static void __init sun5i_ahb_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_factors_clk_setup(node, &sun5i_a13_ahb_data); |
|
} |
|
CLK_OF_DECLARE(sun5i_ahb, "allwinner,sun5i-a13-ahb-clk", |
|
sun5i_ahb_clk_setup); |
|
|
|
static void __init sun6i_ahb1_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_factors_clk_setup(node, &sun6i_ahb1_data); |
|
} |
|
CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk", |
|
sun6i_ahb1_clk_setup); |
|
|
|
static void __init sun4i_apb1_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_factors_clk_setup(node, &sun4i_apb1_data); |
|
} |
|
CLK_OF_DECLARE(sun4i_apb1, "allwinner,sun4i-a10-apb1-clk", |
|
sun4i_apb1_clk_setup); |
|
|
|
static void __init sun7i_out_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_factors_clk_setup(node, &sun7i_a20_out_data); |
|
} |
|
CLK_OF_DECLARE(sun7i_out, "allwinner,sun7i-a20-out-clk", |
|
sun7i_out_clk_setup); |
|
|
|
|
|
/* |
|
* sunxi_mux_clk_setup() - Setup function for muxes |
|
*/ |
|
|
|
#define SUNXI_MUX_GATE_WIDTH 2 |
|
|
|
struct mux_data { |
|
u8 shift; |
|
}; |
|
|
|
static const struct mux_data sun4i_cpu_mux_data __initconst = { |
|
.shift = 16, |
|
}; |
|
|
|
static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = { |
|
.shift = 12, |
|
}; |
|
|
|
static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = { |
|
.shift = 0, |
|
}; |
|
|
|
static struct clk * __init sunxi_mux_clk_setup(struct device_node *node, |
|
const struct mux_data *data, |
|
unsigned long flags) |
|
{ |
|
struct clk *clk; |
|
const char *clk_name = node->name; |
|
const char *parents[SUNXI_MAX_PARENTS]; |
|
void __iomem *reg; |
|
int i; |
|
|
|
reg = of_iomap(node, 0); |
|
if (!reg) { |
|
pr_err("Could not map registers for mux-clk: %pOF\n", node); |
|
return NULL; |
|
} |
|
|
|
i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS); |
|
if (of_property_read_string(node, "clock-output-names", &clk_name)) { |
|
pr_err("%s: could not read clock-output-names from \"%pOF\"\n", |
|
__func__, node); |
|
goto out_unmap; |
|
} |
|
|
|
clk = clk_register_mux(NULL, clk_name, parents, i, |
|
CLK_SET_RATE_PARENT | flags, reg, |
|
data->shift, SUNXI_MUX_GATE_WIDTH, |
|
0, &clk_lock); |
|
|
|
if (IS_ERR(clk)) { |
|
pr_err("%s: failed to register mux clock %s: %ld\n", __func__, |
|
clk_name, PTR_ERR(clk)); |
|
goto out_unmap; |
|
} |
|
|
|
if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) { |
|
pr_err("%s: failed to add clock provider for %s\n", |
|
__func__, clk_name); |
|
clk_unregister_divider(clk); |
|
goto out_unmap; |
|
} |
|
|
|
return clk; |
|
out_unmap: |
|
iounmap(reg); |
|
return NULL; |
|
} |
|
|
|
static void __init sun4i_cpu_clk_setup(struct device_node *node) |
|
{ |
|
/* Protect CPU clock */ |
|
sunxi_mux_clk_setup(node, &sun4i_cpu_mux_data, CLK_IS_CRITICAL); |
|
} |
|
CLK_OF_DECLARE(sun4i_cpu, "allwinner,sun4i-a10-cpu-clk", |
|
sun4i_cpu_clk_setup); |
|
|
|
static void __init sun6i_ahb1_mux_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_mux_clk_setup(node, &sun6i_a31_ahb1_mux_data, 0); |
|
} |
|
CLK_OF_DECLARE(sun6i_ahb1_mux, "allwinner,sun6i-a31-ahb1-mux-clk", |
|
sun6i_ahb1_mux_clk_setup); |
|
|
|
static void __init sun8i_ahb2_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_mux_clk_setup(node, &sun8i_h3_ahb2_mux_data, 0); |
|
} |
|
CLK_OF_DECLARE(sun8i_ahb2, "allwinner,sun8i-h3-ahb2-clk", |
|
sun8i_ahb2_clk_setup); |
|
|
|
|
|
/* |
|
* sunxi_divider_clk_setup() - Setup function for simple divider clocks |
|
*/ |
|
|
|
struct div_data { |
|
u8 shift; |
|
u8 pow; |
|
u8 width; |
|
const struct clk_div_table *table; |
|
}; |
|
|
|
static const struct div_data sun4i_axi_data __initconst = { |
|
.shift = 0, |
|
.pow = 0, |
|
.width = 2, |
|
}; |
|
|
|
static const struct clk_div_table sun8i_a23_axi_table[] __initconst = { |
|
{ .val = 0, .div = 1 }, |
|
{ .val = 1, .div = 2 }, |
|
{ .val = 2, .div = 3 }, |
|
{ .val = 3, .div = 4 }, |
|
{ .val = 4, .div = 4 }, |
|
{ .val = 5, .div = 4 }, |
|
{ .val = 6, .div = 4 }, |
|
{ .val = 7, .div = 4 }, |
|
{ } /* sentinel */ |
|
}; |
|
|
|
static const struct div_data sun8i_a23_axi_data __initconst = { |
|
.width = 3, |
|
.table = sun8i_a23_axi_table, |
|
}; |
|
|
|
static const struct div_data sun4i_ahb_data __initconst = { |
|
.shift = 4, |
|
.pow = 1, |
|
.width = 2, |
|
}; |
|
|
|
static const struct clk_div_table sun4i_apb0_table[] __initconst = { |
|
{ .val = 0, .div = 2 }, |
|
{ .val = 1, .div = 2 }, |
|
{ .val = 2, .div = 4 }, |
|
{ .val = 3, .div = 8 }, |
|
{ } /* sentinel */ |
|
}; |
|
|
|
static const struct div_data sun4i_apb0_data __initconst = { |
|
.shift = 8, |
|
.pow = 1, |
|
.width = 2, |
|
.table = sun4i_apb0_table, |
|
}; |
|
|
|
static void __init sunxi_divider_clk_setup(struct device_node *node, |
|
const struct div_data *data) |
|
{ |
|
struct clk *clk; |
|
const char *clk_name = node->name; |
|
const char *clk_parent; |
|
void __iomem *reg; |
|
|
|
reg = of_iomap(node, 0); |
|
if (!reg) { |
|
pr_err("Could not map registers for mux-clk: %pOF\n", node); |
|
return; |
|
} |
|
|
|
clk_parent = of_clk_get_parent_name(node, 0); |
|
|
|
if (of_property_read_string(node, "clock-output-names", &clk_name)) { |
|
pr_err("%s: could not read clock-output-names from \"%pOF\"\n", |
|
__func__, node); |
|
goto out_unmap; |
|
} |
|
|
|
clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0, |
|
reg, data->shift, data->width, |
|
data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, |
|
data->table, &clk_lock); |
|
if (IS_ERR(clk)) { |
|
pr_err("%s: failed to register divider clock %s: %ld\n", |
|
__func__, clk_name, PTR_ERR(clk)); |
|
goto out_unmap; |
|
} |
|
|
|
if (of_clk_add_provider(node, of_clk_src_simple_get, clk)) { |
|
pr_err("%s: failed to add clock provider for %s\n", |
|
__func__, clk_name); |
|
goto out_unregister; |
|
} |
|
|
|
if (clk_register_clkdev(clk, clk_name, NULL)) { |
|
of_clk_del_provider(node); |
|
goto out_unregister; |
|
} |
|
|
|
return; |
|
out_unregister: |
|
clk_unregister_divider(clk); |
|
|
|
out_unmap: |
|
iounmap(reg); |
|
} |
|
|
|
static void __init sun4i_ahb_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_divider_clk_setup(node, &sun4i_ahb_data); |
|
} |
|
CLK_OF_DECLARE(sun4i_ahb, "allwinner,sun4i-a10-ahb-clk", |
|
sun4i_ahb_clk_setup); |
|
|
|
static void __init sun4i_apb0_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_divider_clk_setup(node, &sun4i_apb0_data); |
|
} |
|
CLK_OF_DECLARE(sun4i_apb0, "allwinner,sun4i-a10-apb0-clk", |
|
sun4i_apb0_clk_setup); |
|
|
|
static void __init sun4i_axi_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_divider_clk_setup(node, &sun4i_axi_data); |
|
} |
|
CLK_OF_DECLARE(sun4i_axi, "allwinner,sun4i-a10-axi-clk", |
|
sun4i_axi_clk_setup); |
|
|
|
static void __init sun8i_axi_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_divider_clk_setup(node, &sun8i_a23_axi_data); |
|
} |
|
CLK_OF_DECLARE(sun8i_axi, "allwinner,sun8i-a23-axi-clk", |
|
sun8i_axi_clk_setup); |
|
|
|
|
|
|
|
/* |
|
* sunxi_gates_clk_setup() - Setup function for leaf gates on clocks |
|
*/ |
|
|
|
#define SUNXI_GATES_MAX_SIZE 64 |
|
|
|
struct gates_data { |
|
DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); |
|
}; |
|
|
|
/* |
|
* sunxi_divs_clk_setup() helper data |
|
*/ |
|
|
|
#define SUNXI_DIVS_MAX_QTY 4 |
|
#define SUNXI_DIVISOR_WIDTH 2 |
|
|
|
struct divs_data { |
|
const struct factors_data *factors; /* data for the factor clock */ |
|
int ndivs; /* number of outputs */ |
|
/* |
|
* List of outputs. Refer to the diagram for sunxi_divs_clk_setup(): |
|
* self or base factor clock refers to the output from the pll |
|
* itself. The remaining refer to fixed or configurable divider |
|
* outputs. |
|
*/ |
|
struct { |
|
u8 self; /* is it the base factor clock? (only one) */ |
|
u8 fixed; /* is it a fixed divisor? if not... */ |
|
struct clk_div_table *table; /* is it a table based divisor? */ |
|
u8 shift; /* otherwise it's a normal divisor with this shift */ |
|
u8 pow; /* is it power-of-two based? */ |
|
u8 gate; /* is it independently gateable? */ |
|
bool critical; |
|
} div[SUNXI_DIVS_MAX_QTY]; |
|
}; |
|
|
|
static struct clk_div_table pll6_sata_tbl[] = { |
|
{ .val = 0, .div = 6, }, |
|
{ .val = 1, .div = 12, }, |
|
{ .val = 2, .div = 18, }, |
|
{ .val = 3, .div = 24, }, |
|
{ } /* sentinel */ |
|
}; |
|
|
|
static const struct divs_data pll5_divs_data __initconst = { |
|
.factors = &sun4i_pll5_data, |
|
.ndivs = 2, |
|
.div = { |
|
/* Protect PLL5_DDR */ |
|
{ .shift = 0, .pow = 0, .critical = true }, /* M, DDR */ |
|
{ .shift = 16, .pow = 1, }, /* P, other */ |
|
/* No output for the base factor clock */ |
|
} |
|
}; |
|
|
|
static const struct divs_data pll6_divs_data __initconst = { |
|
.factors = &sun4i_pll5_data, |
|
.ndivs = 4, |
|
.div = { |
|
{ .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ |
|
{ .fixed = 2 }, /* P, other */ |
|
{ .self = 1 }, /* base factor clock, 2x */ |
|
{ .fixed = 4 }, /* pll6 / 4, used as ahb input */ |
|
} |
|
}; |
|
|
|
static const struct divs_data sun6i_a31_pll6_divs_data __initconst = { |
|
.factors = &sun6i_a31_pll6_data, |
|
.ndivs = 2, |
|
.div = { |
|
{ .fixed = 2 }, /* normal output */ |
|
{ .self = 1 }, /* base factor clock, 2x */ |
|
} |
|
}; |
|
|
|
/* |
|
* sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks |
|
* |
|
* These clocks look something like this |
|
* ________________________ |
|
* | ___divisor 1---|----> to consumer |
|
* parent >--| pll___/___divisor 2---|----> to consumer |
|
* | \_______________|____> to consumer |
|
* |________________________| |
|
*/ |
|
|
|
static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node, |
|
const struct divs_data *data) |
|
{ |
|
struct clk_onecell_data *clk_data; |
|
const char *parent; |
|
const char *clk_name; |
|
struct clk **clks, *pclk; |
|
struct clk_hw *gate_hw, *rate_hw; |
|
const struct clk_ops *rate_ops; |
|
struct clk_gate *gate = NULL; |
|
struct clk_fixed_factor *fix_factor; |
|
struct clk_divider *divider; |
|
struct factors_data factors = *data->factors; |
|
char *derived_name = NULL; |
|
void __iomem *reg; |
|
int ndivs = SUNXI_DIVS_MAX_QTY, i = 0; |
|
int flags, clkflags; |
|
|
|
/* if number of children known, use it */ |
|
if (data->ndivs) |
|
ndivs = data->ndivs; |
|
|
|
/* Try to find a name for base factor clock */ |
|
for (i = 0; i < ndivs; i++) { |
|
if (data->div[i].self) { |
|
of_property_read_string_index(node, "clock-output-names", |
|
i, &factors.name); |
|
break; |
|
} |
|
} |
|
/* If we don't have a .self clk use the first output-name up to '_' */ |
|
if (factors.name == NULL) { |
|
char *endp; |
|
|
|
of_property_read_string_index(node, "clock-output-names", |
|
0, &clk_name); |
|
endp = strchr(clk_name, '_'); |
|
if (endp) { |
|
derived_name = kstrndup(clk_name, endp - clk_name, |
|
GFP_KERNEL); |
|
if (!derived_name) |
|
return NULL; |
|
factors.name = derived_name; |
|
} else { |
|
factors.name = clk_name; |
|
} |
|
} |
|
|
|
/* Set up factor clock that we will be dividing */ |
|
pclk = sunxi_factors_clk_setup(node, &factors); |
|
if (!pclk) |
|
return NULL; |
|
|
|
parent = __clk_get_name(pclk); |
|
kfree(derived_name); |
|
|
|
reg = of_iomap(node, 0); |
|
if (!reg) { |
|
pr_err("Could not map registers for divs-clk: %pOF\n", node); |
|
return NULL; |
|
} |
|
|
|
clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); |
|
if (!clk_data) |
|
goto out_unmap; |
|
|
|
clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL); |
|
if (!clks) |
|
goto free_clkdata; |
|
|
|
clk_data->clks = clks; |
|
|
|
/* It's not a good idea to have automatic reparenting changing |
|
* our RAM clock! */ |
|
clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; |
|
|
|
for (i = 0; i < ndivs; i++) { |
|
if (of_property_read_string_index(node, "clock-output-names", |
|
i, &clk_name) != 0) |
|
break; |
|
|
|
/* If this is the base factor clock, only update clks */ |
|
if (data->div[i].self) { |
|
clk_data->clks[i] = pclk; |
|
continue; |
|
} |
|
|
|
gate_hw = NULL; |
|
rate_hw = NULL; |
|
rate_ops = NULL; |
|
|
|
/* If this leaf clock can be gated, create a gate */ |
|
if (data->div[i].gate) { |
|
gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
|
if (!gate) |
|
goto free_clks; |
|
|
|
gate->reg = reg; |
|
gate->bit_idx = data->div[i].gate; |
|
gate->lock = &clk_lock; |
|
|
|
gate_hw = &gate->hw; |
|
} |
|
|
|
/* Leaves can be fixed or configurable divisors */ |
|
if (data->div[i].fixed) { |
|
fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL); |
|
if (!fix_factor) |
|
goto free_gate; |
|
|
|
fix_factor->mult = 1; |
|
fix_factor->div = data->div[i].fixed; |
|
|
|
rate_hw = &fix_factor->hw; |
|
rate_ops = &clk_fixed_factor_ops; |
|
} else { |
|
divider = kzalloc(sizeof(*divider), GFP_KERNEL); |
|
if (!divider) |
|
goto free_gate; |
|
|
|
flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0; |
|
|
|
divider->reg = reg; |
|
divider->shift = data->div[i].shift; |
|
divider->width = SUNXI_DIVISOR_WIDTH; |
|
divider->flags = flags; |
|
divider->lock = &clk_lock; |
|
divider->table = data->div[i].table; |
|
|
|
rate_hw = ÷r->hw; |
|
rate_ops = &clk_divider_ops; |
|
} |
|
|
|
/* Wrap the (potential) gate and the divisor on a composite |
|
* clock to unify them */ |
|
clks[i] = clk_register_composite(NULL, clk_name, &parent, 1, |
|
NULL, NULL, |
|
rate_hw, rate_ops, |
|
gate_hw, &clk_gate_ops, |
|
clkflags | |
|
(data->div[i].critical ? |
|
CLK_IS_CRITICAL : 0)); |
|
|
|
WARN_ON(IS_ERR(clk_data->clks[i])); |
|
} |
|
|
|
/* Adjust to the real max */ |
|
clk_data->clk_num = i; |
|
|
|
if (of_clk_add_provider(node, of_clk_src_onecell_get, clk_data)) { |
|
pr_err("%s: failed to add clock provider for %s\n", |
|
__func__, clk_name); |
|
goto free_gate; |
|
} |
|
|
|
return clks; |
|
free_gate: |
|
kfree(gate); |
|
free_clks: |
|
kfree(clks); |
|
free_clkdata: |
|
kfree(clk_data); |
|
out_unmap: |
|
iounmap(reg); |
|
return NULL; |
|
} |
|
|
|
static void __init sun4i_pll5_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_divs_clk_setup(node, &pll5_divs_data); |
|
} |
|
CLK_OF_DECLARE(sun4i_pll5, "allwinner,sun4i-a10-pll5-clk", |
|
sun4i_pll5_clk_setup); |
|
|
|
static void __init sun4i_pll6_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_divs_clk_setup(node, &pll6_divs_data); |
|
} |
|
CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk", |
|
sun4i_pll6_clk_setup); |
|
|
|
static void __init sun6i_pll6_clk_setup(struct device_node *node) |
|
{ |
|
sunxi_divs_clk_setup(node, &sun6i_a31_pll6_divs_data); |
|
} |
|
CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk", |
|
sun6i_pll6_clk_setup); |
|
|
|
/* |
|
* sun6i display |
|
* |
|
* rate = parent_rate / (m + 1); |
|
*/ |
|
static void sun6i_display_factors(struct factors_request *req) |
|
{ |
|
u8 m; |
|
|
|
if (req->rate > req->parent_rate) |
|
req->rate = req->parent_rate; |
|
|
|
m = DIV_ROUND_UP(req->parent_rate, req->rate); |
|
|
|
req->rate = req->parent_rate / m; |
|
req->m = m - 1; |
|
} |
|
|
|
static const struct clk_factors_config sun6i_display_config = { |
|
.mshift = 0, |
|
.mwidth = 4, |
|
}; |
|
|
|
static const struct factors_data sun6i_display_data __initconst = { |
|
.enable = 31, |
|
.mux = 24, |
|
.muxmask = BIT(2) | BIT(1) | BIT(0), |
|
.table = &sun6i_display_config, |
|
.getter = sun6i_display_factors, |
|
}; |
|
|
|
static void __init sun6i_display_setup(struct device_node *node) |
|
{ |
|
sunxi_factors_clk_setup(node, &sun6i_display_data); |
|
} |
|
CLK_OF_DECLARE(sun6i_display, "allwinner,sun6i-a31-display-clk", |
|
sun6i_display_setup);
|
|
|