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376 lines
8.8 KiB
376 lines
8.8 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2013 Emilio López |
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* |
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* Emilio López <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include "clk-factors.h" |
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/* |
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* sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks |
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* MOD0 rate is calculated as follows |
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* rate = (parent_rate >> p) / (m + 1); |
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*/ |
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static void sun4i_a10_get_mod0_factors(struct factors_request *req) |
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{ |
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u8 div, calcm, calcp; |
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/* These clocks can only divide, so we will never be able to achieve |
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* frequencies higher than the parent frequency */ |
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if (req->rate > req->parent_rate) |
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req->rate = req->parent_rate; |
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div = DIV_ROUND_UP(req->parent_rate, req->rate); |
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if (div < 16) |
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calcp = 0; |
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else if (div / 2 < 16) |
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calcp = 1; |
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else if (div / 4 < 16) |
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calcp = 2; |
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else |
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calcp = 3; |
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calcm = DIV_ROUND_UP(div, 1 << calcp); |
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req->rate = (req->parent_rate >> calcp) / calcm; |
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req->m = calcm - 1; |
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req->p = calcp; |
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} |
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/* user manual says "n" but it's really "p" */ |
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static const struct clk_factors_config sun4i_a10_mod0_config = { |
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.mshift = 0, |
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.mwidth = 4, |
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.pshift = 16, |
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.pwidth = 2, |
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}; |
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static const struct factors_data sun4i_a10_mod0_data = { |
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.enable = 31, |
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.mux = 24, |
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.muxmask = BIT(1) | BIT(0), |
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.table = &sun4i_a10_mod0_config, |
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.getter = sun4i_a10_get_mod0_factors, |
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}; |
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static DEFINE_SPINLOCK(sun4i_a10_mod0_lock); |
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static void __init sun4i_a10_mod0_setup(struct device_node *node) |
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{ |
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void __iomem *reg; |
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reg = of_iomap(node, 0); |
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if (!reg) { |
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/* |
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* This happens with mod0 clk nodes instantiated through |
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* mfd, as those do not have their resources assigned at |
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* CLK_OF_DECLARE time yet, so do not print an error. |
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*/ |
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return; |
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} |
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sunxi_factors_register(node, &sun4i_a10_mod0_data, |
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&sun4i_a10_mod0_lock, reg); |
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} |
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CLK_OF_DECLARE_DRIVER(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", |
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sun4i_a10_mod0_setup); |
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static int sun4i_a10_mod0_clk_probe(struct platform_device *pdev) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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struct resource *r; |
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void __iomem *reg; |
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if (!np) |
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return -ENODEV; |
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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reg = devm_ioremap_resource(&pdev->dev, r); |
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if (IS_ERR(reg)) |
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return PTR_ERR(reg); |
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sunxi_factors_register(np, &sun4i_a10_mod0_data, |
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&sun4i_a10_mod0_lock, reg); |
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return 0; |
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} |
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static const struct of_device_id sun4i_a10_mod0_clk_dt_ids[] = { |
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{ .compatible = "allwinner,sun4i-a10-mod0-clk" }, |
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{ /* sentinel */ } |
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}; |
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static struct platform_driver sun4i_a10_mod0_clk_driver = { |
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.driver = { |
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.name = "sun4i-a10-mod0-clk", |
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.of_match_table = sun4i_a10_mod0_clk_dt_ids, |
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}, |
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.probe = sun4i_a10_mod0_clk_probe, |
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}; |
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builtin_platform_driver(sun4i_a10_mod0_clk_driver); |
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static const struct factors_data sun9i_a80_mod0_data __initconst = { |
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.enable = 31, |
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.mux = 24, |
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.muxmask = BIT(3) | BIT(2) | BIT(1) | BIT(0), |
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.table = &sun4i_a10_mod0_config, |
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.getter = sun4i_a10_get_mod0_factors, |
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}; |
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static void __init sun9i_a80_mod0_setup(struct device_node *node) |
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{ |
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void __iomem *reg; |
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reg = of_io_request_and_map(node, 0, of_node_full_name(node)); |
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if (IS_ERR(reg)) { |
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pr_err("Could not get registers for mod0-clk: %pOFn\n", |
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node); |
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return; |
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} |
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sunxi_factors_register(node, &sun9i_a80_mod0_data, |
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&sun4i_a10_mod0_lock, reg); |
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} |
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CLK_OF_DECLARE(sun9i_a80_mod0, "allwinner,sun9i-a80-mod0-clk", sun9i_a80_mod0_setup); |
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static DEFINE_SPINLOCK(sun5i_a13_mbus_lock); |
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static void __init sun5i_a13_mbus_setup(struct device_node *node) |
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{ |
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void __iomem *reg; |
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reg = of_iomap(node, 0); |
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if (!reg) { |
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pr_err("Could not get registers for a13-mbus-clk\n"); |
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return; |
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} |
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/* The MBUS clocks needs to be always enabled */ |
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sunxi_factors_register_critical(node, &sun4i_a10_mod0_data, |
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&sun5i_a13_mbus_lock, reg); |
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} |
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CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup); |
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struct mmc_phase { |
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struct clk_hw hw; |
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u8 offset; |
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void __iomem *reg; |
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spinlock_t *lock; |
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}; |
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#define to_mmc_phase(_hw) container_of(_hw, struct mmc_phase, hw) |
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static int mmc_get_phase(struct clk_hw *hw) |
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{ |
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struct clk *mmc, *mmc_parent, *clk = hw->clk; |
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struct mmc_phase *phase = to_mmc_phase(hw); |
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unsigned int mmc_rate, mmc_parent_rate; |
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u16 step, mmc_div; |
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u32 value; |
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u8 delay; |
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value = readl(phase->reg); |
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delay = (value >> phase->offset) & 0x3; |
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if (!delay) |
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return 180; |
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/* Get the main MMC clock */ |
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mmc = clk_get_parent(clk); |
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if (!mmc) |
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return -EINVAL; |
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/* And its rate */ |
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mmc_rate = clk_get_rate(mmc); |
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if (!mmc_rate) |
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return -EINVAL; |
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/* Now, get the MMC parent (most likely some PLL) */ |
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mmc_parent = clk_get_parent(mmc); |
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if (!mmc_parent) |
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return -EINVAL; |
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/* And its rate */ |
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mmc_parent_rate = clk_get_rate(mmc_parent); |
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if (!mmc_parent_rate) |
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return -EINVAL; |
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/* Get MMC clock divider */ |
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mmc_div = mmc_parent_rate / mmc_rate; |
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step = DIV_ROUND_CLOSEST(360, mmc_div); |
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return delay * step; |
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} |
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static int mmc_set_phase(struct clk_hw *hw, int degrees) |
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{ |
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struct clk *mmc, *mmc_parent, *clk = hw->clk; |
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struct mmc_phase *phase = to_mmc_phase(hw); |
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unsigned int mmc_rate, mmc_parent_rate; |
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unsigned long flags; |
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u32 value; |
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u8 delay; |
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/* Get the main MMC clock */ |
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mmc = clk_get_parent(clk); |
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if (!mmc) |
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return -EINVAL; |
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/* And its rate */ |
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mmc_rate = clk_get_rate(mmc); |
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if (!mmc_rate) |
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return -EINVAL; |
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/* Now, get the MMC parent (most likely some PLL) */ |
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mmc_parent = clk_get_parent(mmc); |
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if (!mmc_parent) |
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return -EINVAL; |
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/* And its rate */ |
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mmc_parent_rate = clk_get_rate(mmc_parent); |
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if (!mmc_parent_rate) |
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return -EINVAL; |
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if (degrees != 180) { |
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u16 step, mmc_div; |
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/* Get MMC clock divider */ |
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mmc_div = mmc_parent_rate / mmc_rate; |
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/* |
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* We can only outphase the clocks by multiple of the |
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* PLL's period. |
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* |
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* Since the MMC clock in only a divider, and the |
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* formula to get the outphasing in degrees is deg = |
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* 360 * delta / period |
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* |
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* If we simplify this formula, we can see that the |
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* only thing that we're concerned about is the number |
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* of period we want to outphase our clock from, and |
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* the divider set by the MMC clock. |
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*/ |
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step = DIV_ROUND_CLOSEST(360, mmc_div); |
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delay = DIV_ROUND_CLOSEST(degrees, step); |
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} else { |
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delay = 0; |
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} |
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spin_lock_irqsave(phase->lock, flags); |
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value = readl(phase->reg); |
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value &= ~GENMASK(phase->offset + 3, phase->offset); |
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value |= delay << phase->offset; |
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writel(value, phase->reg); |
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spin_unlock_irqrestore(phase->lock, flags); |
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return 0; |
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} |
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static const struct clk_ops mmc_clk_ops = { |
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.get_phase = mmc_get_phase, |
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.set_phase = mmc_set_phase, |
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}; |
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/* |
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* sunxi_mmc_setup - Common setup function for mmc module clocks |
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* |
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* The only difference between module clocks on different platforms is the |
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* width of the mux register bits and the valid values, which are passed in |
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* through struct factors_data. The phase clocks parts are identical. |
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*/ |
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static void __init sunxi_mmc_setup(struct device_node *node, |
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const struct factors_data *data, |
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spinlock_t *lock) |
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{ |
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struct clk_onecell_data *clk_data; |
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const char *parent; |
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void __iomem *reg; |
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int i; |
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reg = of_io_request_and_map(node, 0, of_node_full_name(node)); |
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if (IS_ERR(reg)) { |
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pr_err("Couldn't map the %pOFn clock registers\n", node); |
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return; |
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} |
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clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL); |
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if (!clk_data) |
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return; |
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clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL); |
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if (!clk_data->clks) |
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goto err_free_data; |
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clk_data->clk_num = 3; |
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clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg); |
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if (!clk_data->clks[0]) |
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goto err_free_clks; |
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parent = __clk_get_name(clk_data->clks[0]); |
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for (i = 1; i < 3; i++) { |
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struct clk_init_data init = { |
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.num_parents = 1, |
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.parent_names = &parent, |
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.ops = &mmc_clk_ops, |
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}; |
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struct mmc_phase *phase; |
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phase = kmalloc(sizeof(*phase), GFP_KERNEL); |
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if (!phase) |
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continue; |
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phase->hw.init = &init; |
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phase->reg = reg; |
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phase->lock = lock; |
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if (i == 1) |
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phase->offset = 8; |
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else |
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phase->offset = 20; |
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if (of_property_read_string_index(node, "clock-output-names", |
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i, &init.name)) |
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init.name = node->name; |
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clk_data->clks[i] = clk_register(NULL, &phase->hw); |
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if (IS_ERR(clk_data->clks[i])) { |
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kfree(phase); |
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continue; |
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} |
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} |
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
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return; |
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err_free_clks: |
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kfree(clk_data->clks); |
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err_free_data: |
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kfree(clk_data); |
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} |
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static DEFINE_SPINLOCK(sun4i_a10_mmc_lock); |
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static void __init sun4i_a10_mmc_setup(struct device_node *node) |
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{ |
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sunxi_mmc_setup(node, &sun4i_a10_mod0_data, &sun4i_a10_mmc_lock); |
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} |
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CLK_OF_DECLARE(sun4i_a10_mmc, "allwinner,sun4i-a10-mmc-clk", sun4i_a10_mmc_setup); |
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static DEFINE_SPINLOCK(sun9i_a80_mmc_lock); |
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static void __init sun9i_a80_mmc_setup(struct device_node *node) |
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{ |
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sunxi_mmc_setup(node, &sun9i_a80_mod0_data, &sun9i_a80_mmc_lock); |
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} |
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CLK_OF_DECLARE(sun9i_a80_mmc, "allwinner,sun9i-a80-mmc-clk", sun9i_a80_mmc_setup);
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