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195 lines
5.2 KiB
195 lines
5.2 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2013 Emilio López |
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* Emilio López <[email protected]> |
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* |
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* Copyright 2015 Maxime Ripard |
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* Maxime Ripard <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/slab.h> |
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#include <dt-bindings/clock/sun4i-a10-pll2.h> |
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#define SUN4I_PLL2_ENABLE 31 |
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#define SUN4I_PLL2_PRE_DIV_SHIFT 0 |
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#define SUN4I_PLL2_PRE_DIV_WIDTH 5 |
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#define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0) |
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#define SUN4I_PLL2_N_SHIFT 8 |
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#define SUN4I_PLL2_N_WIDTH 7 |
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#define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0) |
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#define SUN4I_PLL2_POST_DIV_SHIFT 26 |
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#define SUN4I_PLL2_POST_DIV_WIDTH 4 |
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#define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0) |
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#define SUN4I_PLL2_POST_DIV_VALUE 4 |
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#define SUN4I_PLL2_OUTPUTS 4 |
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static DEFINE_SPINLOCK(sun4i_a10_pll2_lock); |
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static void __init sun4i_pll2_setup(struct device_node *node, |
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int post_div_offset) |
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{ |
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const char *clk_name = node->name, *parent; |
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struct clk **clks, *base_clk, *prediv_clk; |
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struct clk_onecell_data *clk_data; |
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struct clk_multiplier *mult; |
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struct clk_gate *gate; |
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void __iomem *reg; |
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u32 val; |
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reg = of_io_request_and_map(node, 0, of_node_full_name(node)); |
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if (IS_ERR(reg)) |
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return; |
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clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); |
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if (!clk_data) |
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goto err_unmap; |
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clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL); |
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if (!clks) |
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goto err_free_data; |
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parent = of_clk_get_parent_name(node, 0); |
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prediv_clk = clk_register_divider(NULL, "pll2-prediv", |
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parent, 0, reg, |
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SUN4I_PLL2_PRE_DIV_SHIFT, |
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SUN4I_PLL2_PRE_DIV_WIDTH, |
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
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&sun4i_a10_pll2_lock); |
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if (IS_ERR(prediv_clk)) { |
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pr_err("Couldn't register the prediv clock\n"); |
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goto err_free_array; |
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} |
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/* Setup the gate part of the PLL2 */ |
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gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); |
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if (!gate) |
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goto err_unregister_prediv; |
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gate->reg = reg; |
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gate->bit_idx = SUN4I_PLL2_ENABLE; |
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gate->lock = &sun4i_a10_pll2_lock; |
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/* Setup the multiplier part of the PLL2 */ |
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mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL); |
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if (!mult) |
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goto err_free_gate; |
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mult->reg = reg; |
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mult->shift = SUN4I_PLL2_N_SHIFT; |
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mult->width = 7; |
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mult->flags = CLK_MULTIPLIER_ZERO_BYPASS | |
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CLK_MULTIPLIER_ROUND_CLOSEST; |
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mult->lock = &sun4i_a10_pll2_lock; |
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parent = __clk_get_name(prediv_clk); |
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base_clk = clk_register_composite(NULL, "pll2-base", |
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&parent, 1, |
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NULL, NULL, |
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&mult->hw, &clk_multiplier_ops, |
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&gate->hw, &clk_gate_ops, |
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CLK_SET_RATE_PARENT); |
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if (IS_ERR(base_clk)) { |
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pr_err("Couldn't register the base multiplier clock\n"); |
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goto err_free_multiplier; |
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} |
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parent = __clk_get_name(base_clk); |
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/* |
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* PLL2-1x |
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* |
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* This is supposed to have a post divider, but we won't need |
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* to use it, we just need to initialise it to 4, and use a |
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* fixed divider. |
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*/ |
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val = readl(reg); |
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val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT); |
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val |= (SUN4I_PLL2_POST_DIV_VALUE - post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT; |
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writel(val, reg); |
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of_property_read_string_index(node, "clock-output-names", |
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SUN4I_A10_PLL2_1X, &clk_name); |
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clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name, |
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parent, |
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CLK_SET_RATE_PARENT, |
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1, |
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SUN4I_PLL2_POST_DIV_VALUE); |
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WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X])); |
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/* |
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* PLL2-2x |
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* |
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* This clock doesn't use the post divider, and really is just |
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* a fixed divider from the PLL2 base clock. |
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*/ |
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of_property_read_string_index(node, "clock-output-names", |
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SUN4I_A10_PLL2_2X, &clk_name); |
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clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name, |
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parent, |
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CLK_SET_RATE_PARENT, |
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1, 2); |
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WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X])); |
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/* PLL2-4x */ |
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of_property_read_string_index(node, "clock-output-names", |
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SUN4I_A10_PLL2_4X, &clk_name); |
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clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name, |
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parent, |
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CLK_SET_RATE_PARENT, |
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1, 1); |
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WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X])); |
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/* PLL2-8x */ |
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of_property_read_string_index(node, "clock-output-names", |
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SUN4I_A10_PLL2_8X, &clk_name); |
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clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name, |
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parent, |
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CLK_SET_RATE_PARENT, |
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2, 1); |
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WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X])); |
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clk_data->clks = clks; |
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clk_data->clk_num = SUN4I_PLL2_OUTPUTS; |
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
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return; |
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err_free_multiplier: |
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kfree(mult); |
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err_free_gate: |
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kfree(gate); |
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err_unregister_prediv: |
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clk_unregister_divider(prediv_clk); |
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err_free_array: |
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kfree(clks); |
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err_free_data: |
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kfree(clk_data); |
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err_unmap: |
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iounmap(reg); |
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} |
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static void __init sun4i_a10_pll2_setup(struct device_node *node) |
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{ |
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sun4i_pll2_setup(node, 0); |
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} |
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CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk", |
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sun4i_a10_pll2_setup); |
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static void __init sun5i_a13_pll2_setup(struct device_node *node) |
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{ |
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sun4i_pll2_setup(node, 1); |
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} |
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CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk", |
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sun5i_a13_pll2_setup);
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