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167 lines
4.3 KiB
167 lines
4.3 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (c) 2016 Maxime Ripard. All rights reserved. |
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*/ |
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#ifndef _CCU_NM_H_ |
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#define _CCU_NM_H_ |
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#include <linux/clk-provider.h> |
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#include "ccu_common.h" |
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#include "ccu_div.h" |
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#include "ccu_frac.h" |
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#include "ccu_mult.h" |
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#include "ccu_sdm.h" |
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/* |
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* struct ccu_nm - Definition of an N-M clock |
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* |
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* Clocks based on the formula parent * N / M |
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*/ |
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struct ccu_nm { |
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u32 enable; |
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u32 lock; |
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struct ccu_mult_internal n; |
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struct ccu_div_internal m; |
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struct ccu_frac_internal frac; |
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struct ccu_sdm_internal sdm; |
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unsigned int fixed_post_div; |
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unsigned int min_rate; |
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unsigned int max_rate; |
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struct ccu_common common; |
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}; |
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#define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ |
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_nshift, _nwidth, \ |
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_mshift, _mwidth, \ |
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_sdm_table, _sdm_en, \ |
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_sdm_reg, _sdm_reg_en, \ |
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_gate, _lock, _flags) \ |
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struct ccu_nm _struct = { \ |
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.enable = _gate, \ |
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.lock = _lock, \ |
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.n = _SUNXI_CCU_MULT(_nshift, _nwidth), \ |
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.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ |
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.sdm = _SUNXI_CCU_SDM(_sdm_table, _sdm_en, \ |
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_sdm_reg, _sdm_reg_en),\ |
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.common = { \ |
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.reg = _reg, \ |
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.features = CCU_FEATURE_SIGMA_DELTA_MOD, \ |
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.hw.init = CLK_HW_INIT(_name, \ |
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_parent, \ |
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&ccu_nm_ops, \ |
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_flags), \ |
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}, \ |
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} |
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#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ |
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_nshift, _nwidth, \ |
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_mshift, _mwidth, \ |
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_frac_en, _frac_sel, \ |
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_frac_rate_0, _frac_rate_1, \ |
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_gate, _lock, _flags) \ |
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struct ccu_nm _struct = { \ |
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.enable = _gate, \ |
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.lock = _lock, \ |
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.n = _SUNXI_CCU_MULT(_nshift, _nwidth), \ |
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.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ |
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.frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \ |
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_frac_rate_0, \ |
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_frac_rate_1), \ |
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.common = { \ |
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.reg = _reg, \ |
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.features = CCU_FEATURE_FRACTIONAL, \ |
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.hw.init = CLK_HW_INIT(_name, \ |
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_parent, \ |
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&ccu_nm_ops, \ |
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_flags), \ |
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}, \ |
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} |
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#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent, \ |
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_reg, _min_rate, \ |
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_nshift, _nwidth, \ |
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_mshift, _mwidth, \ |
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_frac_en, _frac_sel, \ |
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_frac_rate_0, _frac_rate_1,\ |
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_gate, _lock, _flags) \ |
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struct ccu_nm _struct = { \ |
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.enable = _gate, \ |
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.lock = _lock, \ |
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.n = _SUNXI_CCU_MULT(_nshift, _nwidth), \ |
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.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ |
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.frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \ |
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_frac_rate_0, \ |
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_frac_rate_1), \ |
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.min_rate = _min_rate, \ |
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.common = { \ |
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.reg = _reg, \ |
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.features = CCU_FEATURE_FRACTIONAL, \ |
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.hw.init = CLK_HW_INIT(_name, \ |
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_parent, \ |
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&ccu_nm_ops, \ |
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_flags), \ |
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}, \ |
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} |
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#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \ |
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_parent, _reg, \ |
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_min_rate, _max_rate, \ |
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_nshift, _nwidth, \ |
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_mshift, _mwidth, \ |
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_frac_en, _frac_sel, \ |
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_frac_rate_0, \ |
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_frac_rate_1, \ |
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_gate, _lock, _flags) \ |
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struct ccu_nm _struct = { \ |
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.enable = _gate, \ |
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.lock = _lock, \ |
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.n = _SUNXI_CCU_MULT(_nshift, _nwidth), \ |
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.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ |
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.frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \ |
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_frac_rate_0, \ |
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_frac_rate_1), \ |
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.min_rate = _min_rate, \ |
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.max_rate = _max_rate, \ |
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.common = { \ |
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.reg = _reg, \ |
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.features = CCU_FEATURE_FRACTIONAL, \ |
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.hw.init = CLK_HW_INIT(_name, \ |
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_parent, \ |
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&ccu_nm_ops, \ |
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_flags), \ |
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}, \ |
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} |
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#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ |
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_nshift, _nwidth, \ |
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_mshift, _mwidth, \ |
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_gate, _lock, _flags) \ |
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struct ccu_nm _struct = { \ |
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.enable = _gate, \ |
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.lock = _lock, \ |
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.n = _SUNXI_CCU_MULT(_nshift, _nwidth), \ |
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.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ |
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.common = { \ |
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.reg = _reg, \ |
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.hw.init = CLK_HW_INIT(_name, \ |
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_parent, \ |
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&ccu_nm_ops, \ |
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_flags), \ |
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}, \ |
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} |
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static inline struct ccu_nm *hw_to_ccu_nm(struct clk_hw *hw) |
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{ |
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struct ccu_common *common = hw_to_ccu_common(hw); |
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return container_of(common, struct ccu_nm, common); |
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} |
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extern const struct clk_ops ccu_nm_ops; |
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#endif /* _CCU_NM_H_ */
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