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123 lines
3.2 KiB
123 lines
3.2 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (c) 2016 Maxime Ripard. All rights reserved. |
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*/ |
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#ifndef _CCU_MP_H_ |
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#define _CCU_MP_H_ |
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#include <linux/bitops.h> |
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#include <linux/clk-provider.h> |
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#include "ccu_common.h" |
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#include "ccu_div.h" |
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#include "ccu_mult.h" |
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#include "ccu_mux.h" |
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/* |
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* struct ccu_mp - Definition of an M-P clock |
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* |
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* Clocks based on the formula parent >> P / M |
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*/ |
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struct ccu_mp { |
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u32 enable; |
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struct ccu_div_internal m; |
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struct ccu_div_internal p; |
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struct ccu_mux_internal mux; |
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unsigned int fixed_post_div; |
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struct ccu_common common; |
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}; |
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#define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ |
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_mshift, _mwidth, \ |
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_pshift, _pwidth, \ |
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_muxshift, _muxwidth, \ |
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_gate, _postdiv, _flags) \ |
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struct ccu_mp _struct = { \ |
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.enable = _gate, \ |
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.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ |
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.p = _SUNXI_CCU_DIV(_pshift, _pwidth), \ |
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.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \ |
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.fixed_post_div = _postdiv, \ |
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.common = { \ |
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.reg = _reg, \ |
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.features = CCU_FEATURE_FIXED_POSTDIV, \ |
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.hw.init = CLK_HW_INIT_PARENTS(_name, \ |
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_parents, \ |
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&ccu_mp_ops, \ |
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_flags), \ |
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} \ |
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} |
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#define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ |
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_mshift, _mwidth, \ |
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_pshift, _pwidth, \ |
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_muxshift, _muxwidth, \ |
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_gate, _flags) \ |
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struct ccu_mp _struct = { \ |
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.enable = _gate, \ |
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.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \ |
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.p = _SUNXI_CCU_DIV(_pshift, _pwidth), \ |
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.mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \ |
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.common = { \ |
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.reg = _reg, \ |
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.hw.init = CLK_HW_INIT_PARENTS(_name, \ |
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_parents, \ |
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&ccu_mp_ops, \ |
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_flags), \ |
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} \ |
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} |
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#define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ |
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_mshift, _mwidth, \ |
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_pshift, _pwidth, \ |
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_muxshift, _muxwidth, \ |
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_flags) \ |
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SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ |
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_mshift, _mwidth, \ |
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_pshift, _pwidth, \ |
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_muxshift, _muxwidth, \ |
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0, _flags) |
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static inline struct ccu_mp *hw_to_ccu_mp(struct clk_hw *hw) |
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{ |
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struct ccu_common *common = hw_to_ccu_common(hw); |
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return container_of(common, struct ccu_mp, common); |
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} |
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extern const struct clk_ops ccu_mp_ops; |
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/* |
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* Special class of M-P clock that supports MMC timing modes |
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* |
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* Since the MMC clock registers all follow the same layout, we can |
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* simplify the macro for this particular case. In addition, as |
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* switching modes also affects the output clock rate, we need to |
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* have CLK_GET_RATE_NOCACHE for all these types of clocks. |
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*/ |
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#define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ |
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_flags) \ |
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struct ccu_mp _struct = { \ |
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.enable = BIT(31), \ |
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.m = _SUNXI_CCU_DIV(0, 4), \ |
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.p = _SUNXI_CCU_DIV(16, 2), \ |
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.mux = _SUNXI_CCU_MUX(24, 2), \ |
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.common = { \ |
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.reg = _reg, \ |
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.features = CCU_FEATURE_MMC_TIMING_SWITCH, \ |
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.hw.init = CLK_HW_INIT_PARENTS(_name, \ |
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_parents, \ |
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&ccu_mp_mmc_ops, \ |
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CLK_GET_RATE_NOCACHE | \ |
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_flags), \ |
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} \ |
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} |
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extern const struct clk_ops ccu_mp_mmc_ops; |
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#endif /* _CCU_MP_H_ */
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