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34 lines
748 B
34 lines
748 B
/* SPDX-License-Identifier: GPL-2.0+ */ |
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/* |
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* Copyright 2017 Icenowy Zheng <[email protected]> |
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* |
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*/ |
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#ifndef _CCU_SUNIV_F1C100S_H_ |
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#define _CCU_SUNIV_F1C100S_H_ |
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#include <dt-bindings/clock/suniv-ccu-f1c100s.h> |
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#include <dt-bindings/reset/suniv-ccu-f1c100s.h> |
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#define CLK_PLL_CPU 0 |
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#define CLK_PLL_AUDIO_BASE 1 |
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#define CLK_PLL_AUDIO 2 |
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#define CLK_PLL_AUDIO_2X 3 |
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#define CLK_PLL_AUDIO_4X 4 |
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#define CLK_PLL_AUDIO_8X 5 |
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#define CLK_PLL_VIDEO 6 |
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#define CLK_PLL_VIDEO_2X 7 |
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#define CLK_PLL_VE 8 |
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#define CLK_PLL_DDR0 9 |
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#define CLK_PLL_PERIPH 10 |
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/* CPU clock is exported */ |
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#define CLK_AHB 12 |
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#define CLK_APB 13 |
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/* All bus gates, DRAM gates and mod clocks are exported */ |
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#define CLK_NUMBER (CLK_AVS + 1) |
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#endif /* _CCU_SUNIV_F1C100S_H_ */
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