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48 lines
1008 B
48 lines
1008 B
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Copyright 2016 Chen-Yu Tsai |
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* |
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* Chen-Yu Tsai <[email protected]> |
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*/ |
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#ifndef _CCU_SUN9I_A80_H_ |
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#define _CCU_SUN9I_A80_H_ |
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#include <dt-bindings/clock/sun9i-a80-ccu.h> |
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#include <dt-bindings/reset/sun9i-a80-ccu.h> |
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#define CLK_PLL_C0CPUX 0 |
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#define CLK_PLL_C1CPUX 1 |
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/* pll-audio and pll-periph0 are exported to the PRCM block */ |
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#define CLK_PLL_VE 4 |
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#define CLK_PLL_DDR 5 |
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#define CLK_PLL_VIDEO0 6 |
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#define CLK_PLL_VIDEO1 7 |
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#define CLK_PLL_GPU 8 |
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#define CLK_PLL_DE 9 |
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#define CLK_PLL_ISP 10 |
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#define CLK_PLL_PERIPH1 11 |
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/* The CPUX clocks are exported */ |
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#define CLK_ATB0 14 |
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#define CLK_AXI0 15 |
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#define CLK_ATB1 16 |
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#define CLK_AXI1 17 |
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#define CLK_GTBUS 18 |
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#define CLK_AHB0 19 |
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#define CLK_AHB1 20 |
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#define CLK_AHB2 21 |
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#define CLK_APB0 22 |
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#define CLK_APB1 23 |
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#define CLK_CCI400 24 |
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#define CLK_ATS 25 |
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#define CLK_TRACE 26 |
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/* module clocks and bus gates exported */ |
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#define CLK_NUMBER (CLK_BUS_UART5 + 1) |
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#endif /* _CCU_SUN9I_A80_H_ */
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