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56 lines
1.2 KiB
56 lines
1.2 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Copyright 2016 Maxime Ripard |
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* |
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* Maxime Ripard <[email protected]> |
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*/ |
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#ifndef _CCU_SUN5I_H_ |
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#define _CCU_SUN5I_H_ |
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#include <dt-bindings/clock/sun5i-ccu.h> |
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#include <dt-bindings/reset/sun5i-ccu.h> |
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/* The HOSC is exported */ |
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#define CLK_PLL_CORE 2 |
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#define CLK_PLL_AUDIO_BASE 3 |
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#define CLK_PLL_AUDIO 4 |
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#define CLK_PLL_AUDIO_2X 5 |
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#define CLK_PLL_AUDIO_4X 6 |
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#define CLK_PLL_AUDIO_8X 7 |
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#define CLK_PLL_VIDEO0 8 |
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/* The PLL_VIDEO0_2X is exported for HDMI */ |
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#define CLK_PLL_VE 10 |
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#define CLK_PLL_DDR_BASE 11 |
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#define CLK_PLL_DDR 12 |
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#define CLK_PLL_DDR_OTHER 13 |
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#define CLK_PLL_PERIPH 14 |
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#define CLK_PLL_VIDEO1 15 |
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/* The PLL_VIDEO1_2X is exported for HDMI */ |
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/* The CPU clock is exported */ |
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#define CLK_AXI 18 |
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#define CLK_AHB 19 |
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#define CLK_APB0 20 |
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#define CLK_APB1 21 |
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#define CLK_DRAM_AXI 22 |
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/* AHB gates are exported */ |
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/* APB0 gates are exported */ |
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/* APB1 gates are exported */ |
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/* Modules clocks are exported */ |
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/* USB clocks are exported */ |
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/* GPS clock is exported */ |
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/* DRAM gates are exported */ |
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/* More display modules clocks are exported */ |
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#define CLK_TCON_CH1_SCLK 91 |
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/* The rest of the module clocks are exported */ |
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#define CLK_NUMBER (CLK_IEP + 1) |
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#endif /* _CCU_SUN5I_H_ */
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