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56 lines
1.2 KiB
56 lines
1.2 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright 2016 Icenowy Zheng <[email protected]> |
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*/ |
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#ifndef _CCU_SUN50I_H6_H_ |
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#define _CCU_SUN50I_H6_H_ |
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#include <dt-bindings/clock/sun50i-h6-ccu.h> |
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#include <dt-bindings/reset/sun50i-h6-ccu.h> |
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#define CLK_OSC12M 0 |
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#define CLK_PLL_CPUX 1 |
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#define CLK_PLL_DDR0 2 |
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/* PLL_PERIPH0 exported for PRCM */ |
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#define CLK_PLL_PERIPH0_2X 4 |
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#define CLK_PLL_PERIPH0_4X 5 |
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#define CLK_PLL_PERIPH1 6 |
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#define CLK_PLL_PERIPH1_2X 7 |
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#define CLK_PLL_PERIPH1_4X 8 |
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#define CLK_PLL_GPU 9 |
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#define CLK_PLL_VIDEO0 10 |
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#define CLK_PLL_VIDEO0_4X 11 |
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#define CLK_PLL_VIDEO1 12 |
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#define CLK_PLL_VIDEO1_4X 13 |
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#define CLK_PLL_VE 14 |
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#define CLK_PLL_DE 15 |
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#define CLK_PLL_HSIC 16 |
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#define CLK_PLL_AUDIO_BASE 17 |
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#define CLK_PLL_AUDIO 18 |
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#define CLK_PLL_AUDIO_2X 19 |
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#define CLK_PLL_AUDIO_4X 20 |
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/* CPUX clock exported for DVFS */ |
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#define CLK_AXI 22 |
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#define CLK_CPUX_APB 23 |
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#define CLK_PSI_AHB1_AHB2 24 |
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#define CLK_AHB3 25 |
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/* APB1 clock exported for PIO */ |
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#define CLK_APB2 27 |
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#define CLK_MBUS 28 |
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/* All module clocks and bus gates are exported except DRAM */ |
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#define CLK_DRAM 52 |
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#define CLK_BUS_DRAM 60 |
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#define CLK_NUMBER (CLK_BUS_HDCP + 1) |
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#endif /* _CCU_SUN50I_H6_H_ */
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