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127 lines
3.2 KiB
127 lines
3.2 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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// |
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// Spreadtrum pll clock driver |
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// |
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// Copyright (C) 2015~2017 Spreadtrum, Inc. |
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// Author: Chunyan Zhang <[email protected]> |
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#ifndef _SPRD_PLL_H_ |
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#define _SPRD_PLL_H_ |
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#include "common.h" |
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struct reg_cfg { |
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u32 val; |
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u32 msk; |
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}; |
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struct clk_bit_field { |
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u8 shift; |
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u8 width; |
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}; |
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enum { |
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PLL_LOCK_DONE, |
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PLL_DIV_S, |
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PLL_MOD_EN, |
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PLL_SDM_EN, |
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PLL_REFIN, |
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PLL_IBIAS, |
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PLL_N, |
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PLL_NINT, |
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PLL_KINT, |
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PLL_PREDIV, |
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PLL_POSTDIV, |
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PLL_FACT_MAX |
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}; |
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/* |
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* struct sprd_pll - definition of adjustable pll clock |
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* |
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* @reg: registers used to set the configuration of pll clock, |
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* reg[0] shows how many registers this pll clock uses. |
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* @itable: pll ibias table, itable[0] means how many items this |
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* table includes |
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* @udelay delay time after setting rate |
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* @factors used to calculate the pll clock rate |
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* @fvco: fvco threshold rate |
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* @fflag: fvco flag |
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*/ |
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struct sprd_pll { |
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u32 regs_num; |
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const u64 *itable; |
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const struct clk_bit_field *factors; |
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u16 udelay; |
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u16 k1; |
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u16 k2; |
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u16 fflag; |
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u64 fvco; |
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struct sprd_clk_common common; |
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}; |
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#define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \ |
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_regs_num, _itable, _factors, \ |
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_udelay, _k1, _k2, _fflag, \ |
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_fvco, _fn) \ |
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struct sprd_pll _struct = { \ |
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.regs_num = _regs_num, \ |
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.itable = _itable, \ |
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.factors = _factors, \ |
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.udelay = _udelay, \ |
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.k1 = _k1, \ |
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.k2 = _k2, \ |
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.fflag = _fflag, \ |
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.fvco = _fvco, \ |
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.common = { \ |
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.regmap = NULL, \ |
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.reg = _reg, \ |
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.hw.init = _fn(_name, _parent, \ |
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&sprd_pll_ops, 0),\ |
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}, \ |
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} |
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#define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ |
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_regs_num, _itable, _factors, \ |
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_udelay, _k1, _k2, _fflag, _fvco) \ |
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SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \ |
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_itable, _factors, _udelay, _k1, _k2, \ |
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_fflag, _fvco, CLK_HW_INIT) |
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#define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ |
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_regs_num, _itable, _factors, \ |
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_udelay, _k1, _k2) \ |
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SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ |
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_regs_num, _itable, _factors, \ |
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_udelay, _k1, _k2, 0, 0) |
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#define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ |
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_regs_num, _itable, _factors, _udelay) \ |
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SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ |
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_regs_num, _itable, _factors, \ |
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_udelay, 1000, 1000, 0, 0) |
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#define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \ |
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_itable, _factors, _udelay, _k1, _k2, \ |
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_fflag, _fvco) \ |
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SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \ |
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_itable, _factors, _udelay, _k1, _k2, \ |
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_fflag, _fvco, CLK_HW_INIT_FW_NAME) |
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#define SPRD_PLL_HW(_struct, _name, _parent, _reg, _regs_num, _itable, \ |
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_factors, _udelay, _k1, _k2, _fflag, _fvco) \ |
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SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \ |
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_itable, _factors, _udelay, _k1, _k2, \ |
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_fflag, _fvco, CLK_HW_INIT_HW) |
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static inline struct sprd_pll *hw_to_sprd_pll(struct clk_hw *hw) |
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{ |
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struct sprd_clk_common *common = hw_to_sprd_clk_common(hw); |
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return container_of(common, struct sprd_pll, common); |
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} |
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extern const struct clk_ops sprd_pll_ops; |
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#endif /* _SPRD_PLL_H_ */
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