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89 lines
2.5 KiB
89 lines
2.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2018-2019 SiFive, Inc. |
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* Copyright (C) 2018-2019 Wesley Terpstra |
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* Copyright (C) 2018-2019 Paul Walmsley |
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* Copyright (C) 2020 Zong Li |
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* |
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* The FU540 PRCI implements clock and reset control for the SiFive |
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* FU540-C000 chip. This driver assumes that it has sole control |
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* over all PRCI resources. |
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* |
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* This driver is based on the PRCI driver written by Wesley Terpstra: |
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* https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 |
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* |
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* References: |
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* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" |
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*/ |
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#include <linux/module.h> |
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#include <dt-bindings/clock/sifive-fu540-prci.h> |
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#include "fu540-prci.h" |
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#include "sifive-prci.h" |
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/* PRCI integration data for each WRPLL instance */ |
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static struct __prci_wrpll_data __prci_corepll_data = { |
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.cfg0_offs = PRCI_COREPLLCFG0_OFFSET, |
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.cfg1_offs = PRCI_COREPLLCFG1_OFFSET, |
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.enable_bypass = sifive_prci_coreclksel_use_hfclk, |
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.disable_bypass = sifive_prci_coreclksel_use_corepll, |
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}; |
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static struct __prci_wrpll_data __prci_ddrpll_data = { |
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.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, |
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.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, |
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}; |
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static struct __prci_wrpll_data __prci_gemgxlpll_data = { |
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.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, |
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.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, |
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}; |
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/* Linux clock framework integration */ |
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static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops = { |
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.set_rate = sifive_prci_wrpll_set_rate, |
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.round_rate = sifive_prci_wrpll_round_rate, |
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.recalc_rate = sifive_prci_wrpll_recalc_rate, |
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.enable = sifive_prci_clock_enable, |
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.disable = sifive_prci_clock_disable, |
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.is_enabled = sifive_clk_is_enabled, |
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}; |
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static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops = { |
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.recalc_rate = sifive_prci_wrpll_recalc_rate, |
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}; |
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static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = { |
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.recalc_rate = sifive_prci_tlclksel_recalc_rate, |
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}; |
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/* List of clock controls provided by the PRCI */ |
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struct __prci_clock __prci_init_clocks_fu540[] = { |
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[PRCI_CLK_COREPLL] = { |
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.name = "corepll", |
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.parent_name = "hfclk", |
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.ops = &sifive_fu540_prci_wrpll_clk_ops, |
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.pwd = &__prci_corepll_data, |
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}, |
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[PRCI_CLK_DDRPLL] = { |
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.name = "ddrpll", |
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.parent_name = "hfclk", |
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.ops = &sifive_fu540_prci_wrpll_ro_clk_ops, |
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.pwd = &__prci_ddrpll_data, |
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}, |
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[PRCI_CLK_GEMGXLPLL] = { |
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.name = "gemgxlpll", |
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.parent_name = "hfclk", |
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.ops = &sifive_fu540_prci_wrpll_clk_ops, |
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.pwd = &__prci_gemgxlpll_data, |
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}, |
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[PRCI_CLK_TLCLK] = { |
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.name = "tlclk", |
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.parent_name = "corepll", |
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.ops = &sifive_fu540_prci_tlclksel_clk_ops, |
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}, |
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};
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