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509 lines
12 KiB
509 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* R-Car Gen3 Clock Pulse Generator |
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* |
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* Copyright (C) 2015-2018 Glider bvba |
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* Copyright (C) 2019 Renesas Electronics Corp. |
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* |
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* Based on clk-rcar-gen3.c |
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* |
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* Copyright (C) 2015 Renesas Electronics Corp. |
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*/ |
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#include <linux/bug.h> |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/device.h> |
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#include <linux/err.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/pm.h> |
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#include <linux/slab.h> |
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#include <linux/sys_soc.h> |
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#include "renesas-cpg-mssr.h" |
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#include "rcar-cpg-lib.h" |
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#include "rcar-gen3-cpg.h" |
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#define CPG_PLL0CR 0x00d8 |
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#define CPG_PLL2CR 0x002c |
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#define CPG_PLL4CR 0x01f4 |
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#define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */ |
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/* |
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* Z Clock & Z2 Clock |
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* |
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* Traits of this clock: |
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* prepare - clk_prepare only ensures that parents are prepared |
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* enable - clk_enable only ensures that parents are enabled |
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* rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2 |
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* parent - fixed parent. No clk_set_parent support |
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*/ |
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#define CPG_FRQCRB 0x00000004 |
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#define CPG_FRQCRB_KICK BIT(31) |
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#define CPG_FRQCRC 0x000000e0 |
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struct cpg_z_clk { |
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struct clk_hw hw; |
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void __iomem *reg; |
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void __iomem *kick_reg; |
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unsigned long mask; |
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unsigned int fixed_div; |
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}; |
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#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) |
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static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct cpg_z_clk *zclk = to_z_clk(hw); |
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unsigned int mult; |
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u32 val; |
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val = readl(zclk->reg) & zclk->mask; |
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mult = 32 - (val >> __ffs(zclk->mask)); |
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return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, |
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32 * zclk->fixed_div); |
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} |
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static int cpg_z_clk_determine_rate(struct clk_hw *hw, |
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struct clk_rate_request *req) |
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{ |
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struct cpg_z_clk *zclk = to_z_clk(hw); |
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unsigned int min_mult, max_mult, mult; |
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unsigned long prate; |
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prate = req->best_parent_rate / zclk->fixed_div; |
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min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); |
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max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); |
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if (max_mult < min_mult) |
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return -EINVAL; |
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mult = div64_ul(req->rate * 32ULL, prate); |
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mult = clamp(mult, min_mult, max_mult); |
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req->rate = div_u64((u64)prate * mult, 32); |
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return 0; |
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} |
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static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct cpg_z_clk *zclk = to_z_clk(hw); |
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unsigned int mult; |
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unsigned int i; |
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mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, |
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parent_rate); |
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mult = clamp(mult, 1U, 32U); |
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if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) |
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return -EBUSY; |
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cpg_reg_modify(zclk->reg, zclk->mask, |
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((32 - mult) << __ffs(zclk->mask)) & zclk->mask); |
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/* |
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* Set KICK bit in FRQCRB to update hardware setting and wait for |
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* clock change completion. |
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*/ |
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cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK); |
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/* |
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* Note: There is no HW information about the worst case latency. |
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* |
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* Using experimental measurements, it seems that no more than |
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* ~10 iterations are needed, independently of the CPU rate. |
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* Since this value might be dependent of external xtal rate, pll1 |
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* rate or even the other emulation clocks rate, use 1000 as a |
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* "super" safe value. |
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*/ |
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for (i = 1000; i; i--) { |
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if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) |
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return 0; |
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cpu_relax(); |
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} |
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return -ETIMEDOUT; |
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} |
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static const struct clk_ops cpg_z_clk_ops = { |
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.recalc_rate = cpg_z_clk_recalc_rate, |
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.determine_rate = cpg_z_clk_determine_rate, |
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.set_rate = cpg_z_clk_set_rate, |
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}; |
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static struct clk * __init cpg_z_clk_register(const char *name, |
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const char *parent_name, |
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void __iomem *reg, |
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unsigned int div, |
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unsigned int offset) |
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{ |
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struct clk_init_data init; |
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struct cpg_z_clk *zclk; |
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struct clk *clk; |
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zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); |
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if (!zclk) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &cpg_z_clk_ops; |
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init.flags = 0; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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zclk->reg = reg + CPG_FRQCRC; |
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zclk->kick_reg = reg + CPG_FRQCRB; |
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zclk->hw.init = &init; |
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zclk->mask = GENMASK(offset + 4, offset); |
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zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ |
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clk = clk_register(NULL, &zclk->hw); |
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if (IS_ERR(clk)) |
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kfree(zclk); |
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return clk; |
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} |
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struct rpc_clock { |
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struct clk_divider div; |
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struct clk_gate gate; |
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/* |
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* One notifier covers both RPC and RPCD2 clocks as they are both |
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* controlled by the same RPCCKCR register... |
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*/ |
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struct cpg_simple_notifier csn; |
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}; |
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static const struct clk_div_table cpg_rpcsrc_div_table[] = { |
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{ 2, 5 }, { 3, 6 }, { 0, 0 }, |
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}; |
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static const struct clk_div_table cpg_rpc_div_table[] = { |
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{ 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 }, |
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}; |
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static struct clk * __init cpg_rpc_clk_register(const char *name, |
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void __iomem *base, const char *parent_name, |
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struct raw_notifier_head *notifiers) |
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{ |
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struct rpc_clock *rpc; |
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struct clk *clk; |
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rpc = kzalloc(sizeof(*rpc), GFP_KERNEL); |
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if (!rpc) |
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return ERR_PTR(-ENOMEM); |
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rpc->div.reg = base + CPG_RPCCKCR; |
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rpc->div.width = 3; |
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rpc->div.table = cpg_rpc_div_table; |
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rpc->div.lock = &cpg_lock; |
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rpc->gate.reg = base + CPG_RPCCKCR; |
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rpc->gate.bit_idx = 8; |
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rpc->gate.flags = CLK_GATE_SET_TO_DISABLE; |
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rpc->gate.lock = &cpg_lock; |
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rpc->csn.reg = base + CPG_RPCCKCR; |
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clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, |
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&rpc->div.hw, &clk_divider_ops, |
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&rpc->gate.hw, &clk_gate_ops, |
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CLK_SET_RATE_PARENT); |
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if (IS_ERR(clk)) { |
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kfree(rpc); |
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return clk; |
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} |
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cpg_simple_notifier_register(notifiers, &rpc->csn); |
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return clk; |
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} |
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struct rpcd2_clock { |
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struct clk_fixed_factor fixed; |
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struct clk_gate gate; |
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}; |
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static struct clk * __init cpg_rpcd2_clk_register(const char *name, |
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void __iomem *base, |
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const char *parent_name) |
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{ |
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struct rpcd2_clock *rpcd2; |
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struct clk *clk; |
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rpcd2 = kzalloc(sizeof(*rpcd2), GFP_KERNEL); |
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if (!rpcd2) |
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return ERR_PTR(-ENOMEM); |
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rpcd2->fixed.mult = 1; |
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rpcd2->fixed.div = 2; |
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rpcd2->gate.reg = base + CPG_RPCCKCR; |
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rpcd2->gate.bit_idx = 9; |
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rpcd2->gate.flags = CLK_GATE_SET_TO_DISABLE; |
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rpcd2->gate.lock = &cpg_lock; |
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clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, |
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&rpcd2->fixed.hw, &clk_fixed_factor_ops, |
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&rpcd2->gate.hw, &clk_gate_ops, |
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CLK_SET_RATE_PARENT); |
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if (IS_ERR(clk)) |
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kfree(rpcd2); |
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return clk; |
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} |
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static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; |
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static unsigned int cpg_clk_extalr __initdata; |
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static u32 cpg_mode __initdata; |
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static u32 cpg_quirks __initdata; |
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#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ |
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#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ |
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#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */ |
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static const struct soc_device_attribute cpg_quirks_match[] __initconst = { |
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{ |
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.soc_id = "r8a7795", .revision = "ES1.0", |
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.data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST), |
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}, |
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{ |
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.soc_id = "r8a7795", .revision = "ES1.*", |
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.data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), |
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}, |
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{ |
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.soc_id = "r8a7795", .revision = "ES2.0", |
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.data = (void *)SD_SKIP_FIRST, |
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}, |
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{ |
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.soc_id = "r8a7796", .revision = "ES1.0", |
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.data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST), |
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}, |
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{ |
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.soc_id = "r8a7796", .revision = "ES1.1", |
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.data = (void *)SD_SKIP_FIRST, |
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}, |
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{ /* sentinel */ } |
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}; |
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struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, |
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info, |
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struct clk **clks, void __iomem *base, |
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struct raw_notifier_head *notifiers) |
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{ |
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const struct clk *parent; |
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unsigned int mult = 1; |
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unsigned int div = 1; |
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u32 value; |
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parent = clks[core->parent & 0xffff]; /* some types use high bits */ |
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if (IS_ERR(parent)) |
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return ERR_CAST(parent); |
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switch (core->type) { |
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case CLK_TYPE_GEN3_MAIN: |
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div = cpg_pll_config->extal_div; |
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break; |
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case CLK_TYPE_GEN3_PLL0: |
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/* |
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* PLL0 is a configurable multiplier clock. Register it as a |
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* fixed factor clock for now as there's no generic multiplier |
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* clock implementation and we currently have no need to change |
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* the multiplier value. |
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*/ |
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value = readl(base + CPG_PLL0CR); |
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mult = (((value >> 24) & 0x7f) + 1) * 2; |
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if (cpg_quirks & PLL_ERRATA) |
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mult *= 2; |
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break; |
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case CLK_TYPE_GEN3_PLL1: |
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mult = cpg_pll_config->pll1_mult; |
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div = cpg_pll_config->pll1_div; |
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break; |
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case CLK_TYPE_GEN3_PLL2: |
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/* |
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* PLL2 is a configurable multiplier clock. Register it as a |
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* fixed factor clock for now as there's no generic multiplier |
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* clock implementation and we currently have no need to change |
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* the multiplier value. |
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*/ |
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value = readl(base + CPG_PLL2CR); |
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mult = (((value >> 24) & 0x7f) + 1) * 2; |
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if (cpg_quirks & PLL_ERRATA) |
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mult *= 2; |
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break; |
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case CLK_TYPE_GEN3_PLL3: |
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mult = cpg_pll_config->pll3_mult; |
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div = cpg_pll_config->pll3_div; |
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break; |
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case CLK_TYPE_GEN3_PLL4: |
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/* |
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* PLL4 is a configurable multiplier clock. Register it as a |
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* fixed factor clock for now as there's no generic multiplier |
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* clock implementation and we currently have no need to change |
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* the multiplier value. |
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*/ |
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value = readl(base + CPG_PLL4CR); |
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mult = (((value >> 24) & 0x7f) + 1) * 2; |
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if (cpg_quirks & PLL_ERRATA) |
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mult *= 2; |
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break; |
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case CLK_TYPE_GEN3_SD: |
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return cpg_sd_clk_register(core->name, base, core->offset, |
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__clk_get_name(parent), notifiers, |
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cpg_quirks & SD_SKIP_FIRST); |
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case CLK_TYPE_GEN3_R: |
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if (cpg_quirks & RCKCR_CKSEL) { |
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struct cpg_simple_notifier *csn; |
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csn = kzalloc(sizeof(*csn), GFP_KERNEL); |
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if (!csn) |
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return ERR_PTR(-ENOMEM); |
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csn->reg = base + CPG_RCKCR; |
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/* |
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* RINT is default. |
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* Only if EXTALR is populated, we switch to it. |
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*/ |
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value = readl(csn->reg) & 0x3f; |
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if (clk_get_rate(clks[cpg_clk_extalr])) { |
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parent = clks[cpg_clk_extalr]; |
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value |= CPG_RCKCR_CKSEL; |
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} |
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writel(value, csn->reg); |
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cpg_simple_notifier_register(notifiers, csn); |
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break; |
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} |
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/* Select parent clock of RCLK by MD28 */ |
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if (cpg_mode & BIT(28)) |
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parent = clks[cpg_clk_extalr]; |
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break; |
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case CLK_TYPE_GEN3_MDSEL: |
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/* |
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* Clock selectable between two parents and two fixed dividers |
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* using a mode pin |
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*/ |
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if (cpg_mode & BIT(core->offset)) { |
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div = core->div & 0xffff; |
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} else { |
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parent = clks[core->parent >> 16]; |
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if (IS_ERR(parent)) |
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return ERR_CAST(parent); |
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div = core->div >> 16; |
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} |
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mult = 1; |
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break; |
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case CLK_TYPE_GEN3_Z: |
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return cpg_z_clk_register(core->name, __clk_get_name(parent), |
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base, core->div, core->offset); |
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case CLK_TYPE_GEN3_OSC: |
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/* |
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* Clock combining OSC EXTAL predivider and a fixed divider |
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*/ |
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div = cpg_pll_config->osc_prediv * core->div; |
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break; |
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case CLK_TYPE_GEN3_RCKSEL: |
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/* |
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* Clock selectable between two parents and two fixed dividers |
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* using RCKCR.CKSEL |
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*/ |
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if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) { |
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div = core->div & 0xffff; |
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} else { |
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parent = clks[core->parent >> 16]; |
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if (IS_ERR(parent)) |
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return ERR_CAST(parent); |
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div = core->div >> 16; |
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} |
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break; |
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case CLK_TYPE_GEN3_RPCSRC: |
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return clk_register_divider_table(NULL, core->name, |
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__clk_get_name(parent), 0, |
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base + CPG_RPCCKCR, 3, 2, 0, |
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cpg_rpcsrc_div_table, |
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&cpg_lock); |
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case CLK_TYPE_GEN3_E3_RPCSRC: |
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/* |
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* Register RPCSRC as fixed factor clock based on the |
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* MD[4:1] pins and CPG_RPCCKCR[4:3] register value for |
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* which has been set prior to booting the kernel. |
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*/ |
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value = (readl(base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3; |
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switch (value) { |
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case 0: |
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div = 5; |
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break; |
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case 1: |
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div = 3; |
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break; |
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case 2: |
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parent = clks[core->parent >> 16]; |
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if (IS_ERR(parent)) |
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return ERR_CAST(parent); |
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div = core->div; |
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break; |
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case 3: |
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default: |
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div = 2; |
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break; |
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} |
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break; |
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case CLK_TYPE_GEN3_RPC: |
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return cpg_rpc_clk_register(core->name, base, |
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__clk_get_name(parent), notifiers); |
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case CLK_TYPE_GEN3_RPCD2: |
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return cpg_rpcd2_clk_register(core->name, base, |
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__clk_get_name(parent)); |
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default: |
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return ERR_PTR(-EINVAL); |
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} |
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return clk_register_fixed_factor(NULL, core->name, |
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__clk_get_name(parent), 0, mult, div); |
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} |
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int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, |
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unsigned int clk_extalr, u32 mode) |
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{ |
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const struct soc_device_attribute *attr; |
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cpg_pll_config = config; |
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cpg_clk_extalr = clk_extalr; |
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cpg_mode = mode; |
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attr = soc_device_match(cpg_quirks_match); |
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if (attr) |
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cpg_quirks = (uintptr_t)attr->data; |
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pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks); |
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spin_lock_init(&cpg_lock); |
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return 0; |
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}
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