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394 lines
9.2 KiB
394 lines
9.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* R-Car Gen2 Clock Pulse Generator |
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* |
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* Copyright (C) 2016 Cogent Embedded Inc. |
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*/ |
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#include <linux/bug.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/device.h> |
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#include <linux/err.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/sys_soc.h> |
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#include "renesas-cpg-mssr.h" |
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#include "rcar-gen2-cpg.h" |
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#define CPG_FRQCRB 0x0004 |
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#define CPG_FRQCRB_KICK BIT(31) |
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#define CPG_SDCKCR 0x0074 |
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#define CPG_PLL0CR 0x00d8 |
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#define CPG_PLL0CR_STC_SHIFT 24 |
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#define CPG_PLL0CR_STC_MASK (0x7f << CPG_PLL0CR_STC_SHIFT) |
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#define CPG_FRQCRC 0x00e0 |
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#define CPG_FRQCRC_ZFC_SHIFT 8 |
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#define CPG_FRQCRC_ZFC_MASK (0x1f << CPG_FRQCRC_ZFC_SHIFT) |
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#define CPG_ADSPCKCR 0x025c |
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#define CPG_RCANCKCR 0x0270 |
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static spinlock_t cpg_lock; |
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/* |
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* Z Clock |
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* |
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* Traits of this clock: |
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* prepare - clk_prepare only ensures that parents are prepared |
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* enable - clk_enable only ensures that parents are enabled |
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* rate - rate is adjustable. clk->rate = parent->rate * mult / 32 |
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* parent - fixed parent. No clk_set_parent support |
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*/ |
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struct cpg_z_clk { |
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struct clk_hw hw; |
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void __iomem *reg; |
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void __iomem *kick_reg; |
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}; |
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#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) |
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static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct cpg_z_clk *zclk = to_z_clk(hw); |
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unsigned int mult; |
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unsigned int val; |
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val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT; |
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mult = 32 - val; |
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return div_u64((u64)parent_rate * mult, 32); |
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} |
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static int cpg_z_clk_determine_rate(struct clk_hw *hw, |
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struct clk_rate_request *req) |
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{ |
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unsigned long prate = req->best_parent_rate; |
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unsigned int min_mult, max_mult, mult; |
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min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); |
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max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); |
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if (max_mult < min_mult) |
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return -EINVAL; |
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mult = div64_ul(req->rate * 32ULL, prate); |
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mult = clamp(mult, min_mult, max_mult); |
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req->rate = div_u64((u64)prate * mult, 32); |
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return 0; |
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} |
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static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct cpg_z_clk *zclk = to_z_clk(hw); |
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unsigned int mult; |
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u32 val, kick; |
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unsigned int i; |
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mult = div64_ul(rate * 32ULL, parent_rate); |
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mult = clamp(mult, 1U, 32U); |
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if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) |
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return -EBUSY; |
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val = readl(zclk->reg); |
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val &= ~CPG_FRQCRC_ZFC_MASK; |
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val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT; |
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writel(val, zclk->reg); |
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/* |
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* Set KICK bit in FRQCRB to update hardware setting and wait for |
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* clock change completion. |
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*/ |
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kick = readl(zclk->kick_reg); |
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kick |= CPG_FRQCRB_KICK; |
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writel(kick, zclk->kick_reg); |
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/* |
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* Note: There is no HW information about the worst case latency. |
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* |
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* Using experimental measurements, it seems that no more than |
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* ~10 iterations are needed, independently of the CPU rate. |
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* Since this value might be dependent on external xtal rate, pll1 |
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* rate or even the other emulation clocks rate, use 1000 as a |
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* "super" safe value. |
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*/ |
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for (i = 1000; i; i--) { |
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if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) |
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return 0; |
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cpu_relax(); |
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} |
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return -ETIMEDOUT; |
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} |
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static const struct clk_ops cpg_z_clk_ops = { |
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.recalc_rate = cpg_z_clk_recalc_rate, |
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.determine_rate = cpg_z_clk_determine_rate, |
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.set_rate = cpg_z_clk_set_rate, |
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}; |
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static struct clk * __init cpg_z_clk_register(const char *name, |
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const char *parent_name, |
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void __iomem *base) |
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{ |
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struct clk_init_data init; |
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struct cpg_z_clk *zclk; |
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struct clk *clk; |
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zclk = kzalloc(sizeof(*zclk), GFP_KERNEL); |
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if (!zclk) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &cpg_z_clk_ops; |
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init.flags = 0; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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zclk->reg = base + CPG_FRQCRC; |
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zclk->kick_reg = base + CPG_FRQCRB; |
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zclk->hw.init = &init; |
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clk = clk_register(NULL, &zclk->hw); |
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if (IS_ERR(clk)) |
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kfree(zclk); |
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return clk; |
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} |
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static struct clk * __init cpg_rcan_clk_register(const char *name, |
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const char *parent_name, |
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void __iomem *base) |
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{ |
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struct clk_fixed_factor *fixed; |
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struct clk_gate *gate; |
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struct clk *clk; |
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fixed = kzalloc(sizeof(*fixed), GFP_KERNEL); |
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if (!fixed) |
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return ERR_PTR(-ENOMEM); |
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fixed->mult = 1; |
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fixed->div = 6; |
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gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
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if (!gate) { |
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kfree(fixed); |
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return ERR_PTR(-ENOMEM); |
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} |
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gate->reg = base + CPG_RCANCKCR; |
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gate->bit_idx = 8; |
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gate->flags = CLK_GATE_SET_TO_DISABLE; |
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gate->lock = &cpg_lock; |
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clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, |
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&fixed->hw, &clk_fixed_factor_ops, |
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&gate->hw, &clk_gate_ops, 0); |
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if (IS_ERR(clk)) { |
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kfree(gate); |
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kfree(fixed); |
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} |
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return clk; |
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} |
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/* ADSP divisors */ |
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static const struct clk_div_table cpg_adsp_div_table[] = { |
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{ 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, |
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{ 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 }, |
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{ 10, 36 }, { 11, 48 }, { 0, 0 }, |
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}; |
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static struct clk * __init cpg_adsp_clk_register(const char *name, |
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const char *parent_name, |
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void __iomem *base) |
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{ |
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struct clk_divider *div; |
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struct clk_gate *gate; |
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struct clk *clk; |
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div = kzalloc(sizeof(*div), GFP_KERNEL); |
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if (!div) |
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return ERR_PTR(-ENOMEM); |
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div->reg = base + CPG_ADSPCKCR; |
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div->width = 4; |
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div->table = cpg_adsp_div_table; |
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div->lock = &cpg_lock; |
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gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
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if (!gate) { |
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kfree(div); |
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return ERR_PTR(-ENOMEM); |
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} |
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gate->reg = base + CPG_ADSPCKCR; |
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gate->bit_idx = 8; |
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gate->flags = CLK_GATE_SET_TO_DISABLE; |
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gate->lock = &cpg_lock; |
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clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL, |
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&div->hw, &clk_divider_ops, |
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&gate->hw, &clk_gate_ops, 0); |
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if (IS_ERR(clk)) { |
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kfree(gate); |
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kfree(div); |
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} |
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return clk; |
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} |
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/* SDHI divisors */ |
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static const struct clk_div_table cpg_sdh_div_table[] = { |
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{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, |
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{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, |
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{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 }, |
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}; |
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static const struct clk_div_table cpg_sd01_div_table[] = { |
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{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, |
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{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 }, |
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{ 0, 0 }, |
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}; |
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static const struct rcar_gen2_cpg_pll_config *cpg_pll_config __initdata; |
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static unsigned int cpg_pll0_div __initdata; |
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static u32 cpg_mode __initdata; |
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static u32 cpg_quirks __initdata; |
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#define SD_SKIP_FIRST BIT(0) /* Skip first clock in SD table */ |
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static const struct soc_device_attribute cpg_quirks_match[] __initconst = { |
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{ |
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.soc_id = "r8a77470", |
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.data = (void *)SD_SKIP_FIRST, |
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}, |
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{ /* sentinel */ } |
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}; |
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struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev, |
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info, |
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struct clk **clks, void __iomem *base, |
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struct raw_notifier_head *notifiers) |
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{ |
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const struct clk_div_table *table = NULL; |
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const struct clk *parent; |
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const char *parent_name; |
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unsigned int mult = 1; |
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unsigned int div = 1; |
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unsigned int shift; |
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parent = clks[core->parent]; |
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if (IS_ERR(parent)) |
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return ERR_CAST(parent); |
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parent_name = __clk_get_name(parent); |
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switch (core->type) { |
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/* R-Car Gen2 */ |
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case CLK_TYPE_GEN2_MAIN: |
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div = cpg_pll_config->extal_div; |
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break; |
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case CLK_TYPE_GEN2_PLL0: |
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/* |
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* PLL0 is a configurable multiplier clock except on R-Car |
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* V2H/E2. Register the PLL0 clock as a fixed factor clock for |
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* now as there's no generic multiplier clock implementation and |
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* we currently have no need to change the multiplier value. |
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*/ |
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mult = cpg_pll_config->pll0_mult; |
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div = cpg_pll0_div; |
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if (!mult) { |
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u32 pll0cr = readl(base + CPG_PLL0CR); |
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mult = (((pll0cr & CPG_PLL0CR_STC_MASK) >> |
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CPG_PLL0CR_STC_SHIFT) + 1) * 2; |
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} |
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break; |
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case CLK_TYPE_GEN2_PLL1: |
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mult = cpg_pll_config->pll1_mult / 2; |
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break; |
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case CLK_TYPE_GEN2_PLL3: |
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mult = cpg_pll_config->pll3_mult; |
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break; |
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case CLK_TYPE_GEN2_Z: |
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return cpg_z_clk_register(core->name, parent_name, base); |
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case CLK_TYPE_GEN2_LB: |
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div = cpg_mode & BIT(18) ? 36 : 24; |
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break; |
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case CLK_TYPE_GEN2_ADSP: |
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return cpg_adsp_clk_register(core->name, parent_name, base); |
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case CLK_TYPE_GEN2_SDH: |
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table = cpg_sdh_div_table; |
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shift = 8; |
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break; |
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case CLK_TYPE_GEN2_SD0: |
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table = cpg_sd01_div_table; |
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if (cpg_quirks & SD_SKIP_FIRST) |
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table++; |
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shift = 4; |
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break; |
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case CLK_TYPE_GEN2_SD1: |
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table = cpg_sd01_div_table; |
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if (cpg_quirks & SD_SKIP_FIRST) |
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table++; |
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shift = 0; |
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break; |
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case CLK_TYPE_GEN2_QSPI: |
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div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2) ? |
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8 : 10; |
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break; |
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case CLK_TYPE_GEN2_RCAN: |
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return cpg_rcan_clk_register(core->name, parent_name, base); |
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default: |
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return ERR_PTR(-EINVAL); |
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} |
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if (!table) |
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return clk_register_fixed_factor(NULL, core->name, parent_name, |
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0, mult, div); |
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else |
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return clk_register_divider_table(NULL, core->name, |
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parent_name, 0, |
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base + CPG_SDCKCR, shift, 4, |
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0, table, &cpg_lock); |
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} |
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int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config, |
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unsigned int pll0_div, u32 mode) |
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{ |
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const struct soc_device_attribute *attr; |
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cpg_pll_config = config; |
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cpg_pll0_div = pll0_div; |
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cpg_mode = mode; |
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attr = soc_device_match(cpg_quirks_match); |
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if (attr) |
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cpg_quirks = (uintptr_t)attr->data; |
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pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks); |
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spin_lock_init(&cpg_lock); |
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return 0; |
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}
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