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238 lines
5.2 KiB
238 lines
5.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* r8a73a4 Core CPG Clocks |
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* |
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* Copyright (C) 2014 Ulrich Hecht |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/clk/renesas.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/slab.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/spinlock.h> |
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struct r8a73a4_cpg { |
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struct clk_onecell_data data; |
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spinlock_t lock; |
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void __iomem *reg; |
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}; |
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#define CPG_CKSCR 0xc0 |
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#define CPG_FRQCRA 0x00 |
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#define CPG_FRQCRB 0x04 |
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#define CPG_FRQCRC 0xe0 |
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#define CPG_PLL0CR 0xd8 |
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#define CPG_PLL1CR 0x28 |
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#define CPG_PLL2CR 0x2c |
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#define CPG_PLL2HCR 0xe4 |
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#define CPG_PLL2SCR 0xf4 |
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#define CLK_ENABLE_ON_INIT BIT(0) |
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struct div4_clk { |
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const char *name; |
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unsigned int reg; |
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unsigned int shift; |
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}; |
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static struct div4_clk div4_clks[] = { |
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{ "i", CPG_FRQCRA, 20 }, |
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{ "m3", CPG_FRQCRA, 12 }, |
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{ "b", CPG_FRQCRA, 8 }, |
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{ "m1", CPG_FRQCRA, 4 }, |
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{ "m2", CPG_FRQCRA, 0 }, |
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{ "zx", CPG_FRQCRB, 12 }, |
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{ "zs", CPG_FRQCRB, 8 }, |
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{ "hp", CPG_FRQCRB, 4 }, |
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{ NULL, 0, 0 }, |
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}; |
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static const struct clk_div_table div4_div_table[] = { |
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{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 }, |
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{ 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 }, |
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{ 12, 10 }, { 0, 0 } |
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}; |
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static struct clk * __init |
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r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, |
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const char *name) |
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{ |
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const struct clk_div_table *table = NULL; |
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const char *parent_name; |
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unsigned int shift, reg; |
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unsigned int mult = 1; |
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unsigned int div = 1; |
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if (!strcmp(name, "main")) { |
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u32 ckscr = readl(cpg->reg + CPG_CKSCR); |
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switch ((ckscr >> 28) & 3) { |
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case 0: /* extal1 */ |
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parent_name = of_clk_get_parent_name(np, 0); |
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break; |
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case 1: /* extal1 / 2 */ |
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parent_name = of_clk_get_parent_name(np, 0); |
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div = 2; |
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break; |
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case 2: /* extal2 */ |
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parent_name = of_clk_get_parent_name(np, 1); |
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break; |
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case 3: /* extal2 / 2 */ |
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parent_name = of_clk_get_parent_name(np, 1); |
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div = 2; |
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break; |
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} |
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} else if (!strcmp(name, "pll0")) { |
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/* PLL0/1 are configurable multiplier clocks. Register them as |
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* fixed factor clocks for now as there's no generic multiplier |
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* clock implementation and we currently have no need to change |
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* the multiplier value. |
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*/ |
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u32 value = readl(cpg->reg + CPG_PLL0CR); |
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parent_name = "main"; |
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mult = ((value >> 24) & 0x7f) + 1; |
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if (value & BIT(20)) |
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div = 2; |
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} else if (!strcmp(name, "pll1")) { |
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u32 value = readl(cpg->reg + CPG_PLL1CR); |
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parent_name = "main"; |
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/* XXX: enable bit? */ |
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mult = ((value >> 24) & 0x7f) + 1; |
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if (value & BIT(7)) |
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div = 2; |
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} else if (!strncmp(name, "pll2", 4)) { |
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u32 value, cr; |
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switch (name[4]) { |
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case 0: |
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cr = CPG_PLL2CR; |
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break; |
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case 's': |
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cr = CPG_PLL2SCR; |
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break; |
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case 'h': |
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cr = CPG_PLL2HCR; |
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break; |
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default: |
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return ERR_PTR(-EINVAL); |
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} |
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value = readl(cpg->reg + cr); |
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switch ((value >> 5) & 7) { |
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case 0: |
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parent_name = "main"; |
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div = 2; |
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break; |
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case 1: |
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parent_name = "extal2"; |
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div = 2; |
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break; |
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case 3: |
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parent_name = "extal2"; |
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div = 4; |
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break; |
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case 4: |
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parent_name = "main"; |
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break; |
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case 5: |
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parent_name = "extal2"; |
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break; |
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default: |
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pr_warn("%s: unexpected parent of %s\n", __func__, |
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name); |
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return ERR_PTR(-EINVAL); |
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} |
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/* XXX: enable bit? */ |
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mult = ((value >> 24) & 0x7f) + 1; |
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} else if (!strcmp(name, "z") || !strcmp(name, "z2")) { |
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u32 shift = 8; |
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parent_name = "pll0"; |
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if (name[1] == '2') { |
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div = 2; |
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shift = 0; |
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} |
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div *= 32; |
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mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f); |
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} else { |
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struct div4_clk *c; |
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for (c = div4_clks; c->name; c++) { |
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if (!strcmp(name, c->name)) |
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break; |
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} |
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if (!c->name) |
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return ERR_PTR(-EINVAL); |
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parent_name = "pll1"; |
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table = div4_div_table; |
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reg = c->reg; |
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shift = c->shift; |
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} |
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if (!table) { |
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return clk_register_fixed_factor(NULL, name, parent_name, 0, |
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mult, div); |
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} else { |
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return clk_register_divider_table(NULL, name, parent_name, 0, |
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cpg->reg + reg, shift, 4, 0, |
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table, &cpg->lock); |
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} |
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} |
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static void __init r8a73a4_cpg_clocks_init(struct device_node *np) |
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{ |
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struct r8a73a4_cpg *cpg; |
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struct clk **clks; |
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unsigned int i; |
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int num_clks; |
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num_clks = of_property_count_strings(np, "clock-output-names"); |
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if (num_clks < 0) { |
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pr_err("%s: failed to count clocks\n", __func__); |
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return; |
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} |
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cpg = kzalloc(sizeof(*cpg), GFP_KERNEL); |
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clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL); |
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if (cpg == NULL || clks == NULL) { |
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/* We're leaking memory on purpose, there's no point in cleaning |
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* up as the system won't boot anyway. |
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*/ |
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return; |
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} |
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spin_lock_init(&cpg->lock); |
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cpg->data.clks = clks; |
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cpg->data.clk_num = num_clks; |
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cpg->reg = of_iomap(np, 0); |
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if (WARN_ON(cpg->reg == NULL)) |
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return; |
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for (i = 0; i < num_clks; ++i) { |
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const char *name; |
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struct clk *clk; |
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of_property_read_string_index(np, "clock-output-names", i, |
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&name); |
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clk = r8a73a4_cpg_register_clock(np, cpg, name); |
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if (IS_ERR(clk)) |
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pr_err("%s: failed to register %pOFn %s clock (%ld)\n", |
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__func__, np, name, PTR_ERR(clk)); |
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else |
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cpg->data.clks[i] = clk; |
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} |
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of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data); |
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} |
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CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks", |
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r8a73a4_cpg_clocks_init);
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