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138 lines
3.1 KiB
138 lines
3.1 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2014 Google, Inc. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/kernel.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/slab.h> |
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#include "clk.h" |
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struct pistachio_clk_provider * |
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pistachio_clk_alloc_provider(struct device_node *node, unsigned int num_clks) |
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{ |
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struct pistachio_clk_provider *p; |
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p = kzalloc(sizeof(*p), GFP_KERNEL); |
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if (!p) |
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return p; |
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p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL); |
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if (!p->clk_data.clks) |
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goto free_provider; |
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p->clk_data.clk_num = num_clks; |
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p->node = node; |
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p->base = of_iomap(node, 0); |
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if (!p->base) { |
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pr_err("Failed to map clock provider registers\n"); |
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goto free_clks; |
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} |
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return p; |
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free_clks: |
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kfree(p->clk_data.clks); |
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free_provider: |
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kfree(p); |
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return NULL; |
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} |
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void pistachio_clk_register_provider(struct pistachio_clk_provider *p) |
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{ |
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unsigned int i; |
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for (i = 0; i < p->clk_data.clk_num; i++) { |
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if (IS_ERR(p->clk_data.clks[i])) |
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pr_warn("Failed to register clock %d: %ld\n", i, |
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PTR_ERR(p->clk_data.clks[i])); |
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} |
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of_clk_add_provider(p->node, of_clk_src_onecell_get, &p->clk_data); |
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} |
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void pistachio_clk_register_gate(struct pistachio_clk_provider *p, |
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struct pistachio_gate *gate, |
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unsigned int num) |
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{ |
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struct clk *clk; |
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unsigned int i; |
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for (i = 0; i < num; i++) { |
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clk = clk_register_gate(NULL, gate[i].name, gate[i].parent, |
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CLK_SET_RATE_PARENT, |
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p->base + gate[i].reg, gate[i].shift, |
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0, NULL); |
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p->clk_data.clks[gate[i].id] = clk; |
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} |
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} |
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void pistachio_clk_register_mux(struct pistachio_clk_provider *p, |
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struct pistachio_mux *mux, |
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unsigned int num) |
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{ |
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struct clk *clk; |
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unsigned int i; |
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for (i = 0; i < num; i++) { |
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clk = clk_register_mux(NULL, mux[i].name, mux[i].parents, |
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mux[i].num_parents, |
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CLK_SET_RATE_NO_REPARENT, |
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p->base + mux[i].reg, mux[i].shift, |
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get_count_order(mux[i].num_parents), |
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0, NULL); |
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p->clk_data.clks[mux[i].id] = clk; |
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} |
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} |
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void pistachio_clk_register_div(struct pistachio_clk_provider *p, |
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struct pistachio_div *div, |
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unsigned int num) |
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{ |
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struct clk *clk; |
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unsigned int i; |
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for (i = 0; i < num; i++) { |
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clk = clk_register_divider(NULL, div[i].name, div[i].parent, |
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0, p->base + div[i].reg, 0, |
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div[i].width, div[i].div_flags, |
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NULL); |
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p->clk_data.clks[div[i].id] = clk; |
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} |
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} |
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void pistachio_clk_register_fixed_factor(struct pistachio_clk_provider *p, |
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struct pistachio_fixed_factor *ff, |
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unsigned int num) |
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{ |
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struct clk *clk; |
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unsigned int i; |
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for (i = 0; i < num; i++) { |
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clk = clk_register_fixed_factor(NULL, ff[i].name, ff[i].parent, |
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0, 1, ff[i].div); |
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p->clk_data.clks[ff[i].id] = clk; |
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} |
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} |
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void pistachio_clk_force_enable(struct pistachio_clk_provider *p, |
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unsigned int *clk_ids, unsigned int num) |
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{ |
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unsigned int i; |
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int err; |
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for (i = 0; i < num; i++) { |
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struct clk *clk = p->clk_data.clks[clk_ids[i]]; |
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if (IS_ERR(clk)) |
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continue; |
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err = clk_prepare_enable(clk); |
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if (err) |
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pr_err("Failed to enable clock %s: %d\n", |
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__clk_get_name(clk), err); |
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} |
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}
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