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228 lines
5.6 KiB
228 lines
5.6 KiB
/* |
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* Clk driver for NXP LPC18xx/43xx Configuration Registers (CREG) |
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* |
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* Copyright (C) 2015 Joachim Eastwood <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/kernel.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#define LPC18XX_CREG_CREG0 0x004 |
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#define LPC18XX_CREG_CREG0_EN1KHZ BIT(0) |
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#define LPC18XX_CREG_CREG0_EN32KHZ BIT(1) |
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#define LPC18XX_CREG_CREG0_RESET32KHZ BIT(2) |
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#define LPC18XX_CREG_CREG0_PD32KHZ BIT(3) |
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#define to_clk_creg(_hw) container_of(_hw, struct clk_creg_data, hw) |
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enum { |
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CREG_CLK_1KHZ, |
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CREG_CLK_32KHZ, |
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CREG_CLK_MAX, |
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}; |
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struct clk_creg_data { |
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struct clk_hw hw; |
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const char *name; |
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struct regmap *reg; |
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unsigned int en_mask; |
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const struct clk_ops *ops; |
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}; |
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#define CREG_CLK(_name, _emask, _ops) \ |
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{ \ |
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.name = _name, \ |
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.en_mask = LPC18XX_CREG_CREG0_##_emask, \ |
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.ops = &_ops, \ |
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} |
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static int clk_creg_32k_prepare(struct clk_hw *hw) |
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{ |
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struct clk_creg_data *creg = to_clk_creg(hw); |
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int ret; |
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ret = regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, |
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LPC18XX_CREG_CREG0_PD32KHZ | |
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LPC18XX_CREG_CREG0_RESET32KHZ, 0); |
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/* |
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* Powering up the 32k oscillator takes a long while |
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* and sadly there aren't any status bit to poll. |
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*/ |
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msleep(2500); |
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return ret; |
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} |
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static void clk_creg_32k_unprepare(struct clk_hw *hw) |
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{ |
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struct clk_creg_data *creg = to_clk_creg(hw); |
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regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, |
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LPC18XX_CREG_CREG0_PD32KHZ, |
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LPC18XX_CREG_CREG0_PD32KHZ); |
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} |
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static int clk_creg_32k_is_prepared(struct clk_hw *hw) |
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{ |
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struct clk_creg_data *creg = to_clk_creg(hw); |
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u32 reg; |
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regmap_read(creg->reg, LPC18XX_CREG_CREG0, ®); |
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return !(reg & LPC18XX_CREG_CREG0_PD32KHZ) && |
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!(reg & LPC18XX_CREG_CREG0_RESET32KHZ); |
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} |
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static unsigned long clk_creg_1k_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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return parent_rate / 32; |
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} |
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static int clk_creg_enable(struct clk_hw *hw) |
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{ |
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struct clk_creg_data *creg = to_clk_creg(hw); |
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return regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, |
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creg->en_mask, creg->en_mask); |
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} |
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static void clk_creg_disable(struct clk_hw *hw) |
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{ |
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struct clk_creg_data *creg = to_clk_creg(hw); |
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regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, |
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creg->en_mask, 0); |
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} |
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static int clk_creg_is_enabled(struct clk_hw *hw) |
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{ |
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struct clk_creg_data *creg = to_clk_creg(hw); |
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u32 reg; |
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regmap_read(creg->reg, LPC18XX_CREG_CREG0, ®); |
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return !!(reg & creg->en_mask); |
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} |
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static const struct clk_ops clk_creg_32k = { |
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.enable = clk_creg_enable, |
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.disable = clk_creg_disable, |
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.is_enabled = clk_creg_is_enabled, |
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.prepare = clk_creg_32k_prepare, |
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.unprepare = clk_creg_32k_unprepare, |
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.is_prepared = clk_creg_32k_is_prepared, |
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}; |
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static const struct clk_ops clk_creg_1k = { |
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.enable = clk_creg_enable, |
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.disable = clk_creg_disable, |
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.is_enabled = clk_creg_is_enabled, |
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.recalc_rate = clk_creg_1k_recalc_rate, |
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}; |
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static struct clk_creg_data clk_creg_clocks[] = { |
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[CREG_CLK_1KHZ] = CREG_CLK("1khz_clk", EN1KHZ, clk_creg_1k), |
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[CREG_CLK_32KHZ] = CREG_CLK("32khz_clk", EN32KHZ, clk_creg_32k), |
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}; |
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static struct clk *clk_register_creg_clk(struct device *dev, |
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struct clk_creg_data *creg_clk, |
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const char **parent_name, |
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struct regmap *syscon) |
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{ |
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struct clk_init_data init; |
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init.ops = creg_clk->ops; |
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init.name = creg_clk->name; |
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init.parent_names = parent_name; |
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init.num_parents = 1; |
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init.flags = 0; |
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creg_clk->reg = syscon; |
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creg_clk->hw.init = &init; |
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if (dev) |
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return devm_clk_register(dev, &creg_clk->hw); |
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return clk_register(NULL, &creg_clk->hw); |
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} |
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static struct clk *clk_creg_early[CREG_CLK_MAX]; |
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static struct clk_onecell_data clk_creg_early_data = { |
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.clks = clk_creg_early, |
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.clk_num = CREG_CLK_MAX, |
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}; |
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static void __init lpc18xx_creg_clk_init(struct device_node *np) |
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{ |
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const char *clk_32khz_parent; |
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struct regmap *syscon; |
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syscon = syscon_node_to_regmap(np->parent); |
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if (IS_ERR(syscon)) { |
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pr_err("%s: syscon lookup failed\n", __func__); |
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return; |
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} |
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clk_32khz_parent = of_clk_get_parent_name(np, 0); |
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clk_creg_early[CREG_CLK_32KHZ] = |
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clk_register_creg_clk(NULL, &clk_creg_clocks[CREG_CLK_32KHZ], |
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&clk_32khz_parent, syscon); |
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clk_creg_early[CREG_CLK_1KHZ] = ERR_PTR(-EPROBE_DEFER); |
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_creg_early_data); |
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} |
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CLK_OF_DECLARE_DRIVER(lpc18xx_creg_clk, "nxp,lpc1850-creg-clk", |
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lpc18xx_creg_clk_init); |
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static struct clk *clk_creg[CREG_CLK_MAX]; |
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static struct clk_onecell_data clk_creg_data = { |
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.clks = clk_creg, |
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.clk_num = CREG_CLK_MAX, |
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}; |
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static int lpc18xx_creg_clk_probe(struct platform_device *pdev) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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struct regmap *syscon; |
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syscon = syscon_node_to_regmap(np->parent); |
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if (IS_ERR(syscon)) { |
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dev_err(&pdev->dev, "syscon lookup failed\n"); |
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return PTR_ERR(syscon); |
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} |
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clk_creg[CREG_CLK_32KHZ] = clk_creg_early[CREG_CLK_32KHZ]; |
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clk_creg[CREG_CLK_1KHZ] = |
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clk_register_creg_clk(NULL, &clk_creg_clocks[CREG_CLK_1KHZ], |
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&clk_creg_clocks[CREG_CLK_32KHZ].name, |
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syscon); |
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return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_creg_data); |
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} |
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static const struct of_device_id lpc18xx_creg_clk_of_match[] = { |
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{ .compatible = "nxp,lpc1850-creg-clk" }, |
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{}, |
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}; |
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static struct platform_driver lpc18xx_creg_clk_driver = { |
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.probe = lpc18xx_creg_clk_probe, |
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.driver = { |
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.name = "lpc18xx-creg-clk", |
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.of_match_table = lpc18xx_creg_clk_of_match, |
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}, |
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}; |
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builtin_platform_driver(lpc18xx_creg_clk_driver);
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