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671 lines
19 KiB
671 lines
19 KiB
/* |
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* Clk driver for NXP LPC18xx/LPC43xx Clock Generation Unit (CGU) |
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* |
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* Copyright (C) 2015 Joachim Eastwood <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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|
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <dt-bindings/clock/lpc18xx-cgu.h> |
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/* Clock Generation Unit (CGU) registers */ |
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#define LPC18XX_CGU_XTAL_OSC_CTRL 0x018 |
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#define LPC18XX_CGU_PLL0USB_STAT 0x01c |
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#define LPC18XX_CGU_PLL0USB_CTRL 0x020 |
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#define LPC18XX_CGU_PLL0USB_MDIV 0x024 |
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#define LPC18XX_CGU_PLL0USB_NP_DIV 0x028 |
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#define LPC18XX_CGU_PLL0AUDIO_STAT 0x02c |
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#define LPC18XX_CGU_PLL0AUDIO_CTRL 0x030 |
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#define LPC18XX_CGU_PLL0AUDIO_MDIV 0x034 |
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#define LPC18XX_CGU_PLL0AUDIO_NP_DIV 0x038 |
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#define LPC18XX_CGU_PLL0AUDIO_FRAC 0x03c |
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#define LPC18XX_CGU_PLL1_STAT 0x040 |
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#define LPC18XX_CGU_PLL1_CTRL 0x044 |
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#define LPC18XX_PLL1_CTRL_FBSEL BIT(6) |
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#define LPC18XX_PLL1_CTRL_DIRECT BIT(7) |
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#define LPC18XX_CGU_IDIV_CTRL(n) (0x048 + (n) * sizeof(u32)) |
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#define LPC18XX_CGU_BASE_CLK(id) (0x05c + (id) * sizeof(u32)) |
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#define LPC18XX_CGU_PLL_CTRL_OFFSET 0x4 |
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/* PLL0 bits common to both audio and USB PLL */ |
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#define LPC18XX_PLL0_STAT_LOCK BIT(0) |
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#define LPC18XX_PLL0_CTRL_PD BIT(0) |
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#define LPC18XX_PLL0_CTRL_BYPASS BIT(1) |
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#define LPC18XX_PLL0_CTRL_DIRECTI BIT(2) |
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#define LPC18XX_PLL0_CTRL_DIRECTO BIT(3) |
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#define LPC18XX_PLL0_CTRL_CLKEN BIT(4) |
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#define LPC18XX_PLL0_MDIV_MDEC_MASK 0x1ffff |
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#define LPC18XX_PLL0_MDIV_SELP_SHIFT 17 |
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#define LPC18XX_PLL0_MDIV_SELI_SHIFT 22 |
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#define LPC18XX_PLL0_MSEL_MAX BIT(15) |
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/* Register value that gives PLL0 post/pre dividers equal to 1 */ |
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#define LPC18XX_PLL0_NP_DIVS_1 0x00302062 |
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enum { |
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CLK_SRC_OSC32, |
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CLK_SRC_IRC, |
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CLK_SRC_ENET_RX_CLK, |
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CLK_SRC_ENET_TX_CLK, |
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CLK_SRC_GP_CLKIN, |
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CLK_SRC_RESERVED1, |
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CLK_SRC_OSC, |
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CLK_SRC_PLL0USB, |
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CLK_SRC_PLL0AUDIO, |
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CLK_SRC_PLL1, |
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CLK_SRC_RESERVED2, |
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CLK_SRC_RESERVED3, |
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CLK_SRC_IDIVA, |
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CLK_SRC_IDIVB, |
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CLK_SRC_IDIVC, |
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CLK_SRC_IDIVD, |
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CLK_SRC_IDIVE, |
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CLK_SRC_MAX |
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}; |
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static const char *clk_src_names[CLK_SRC_MAX] = { |
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[CLK_SRC_OSC32] = "osc32", |
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[CLK_SRC_IRC] = "irc", |
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[CLK_SRC_ENET_RX_CLK] = "enet_rx_clk", |
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[CLK_SRC_ENET_TX_CLK] = "enet_tx_clk", |
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[CLK_SRC_GP_CLKIN] = "gp_clkin", |
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[CLK_SRC_OSC] = "osc", |
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[CLK_SRC_PLL0USB] = "pll0usb", |
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[CLK_SRC_PLL0AUDIO] = "pll0audio", |
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[CLK_SRC_PLL1] = "pll1", |
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[CLK_SRC_IDIVA] = "idiva", |
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[CLK_SRC_IDIVB] = "idivb", |
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[CLK_SRC_IDIVC] = "idivc", |
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[CLK_SRC_IDIVD] = "idivd", |
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[CLK_SRC_IDIVE] = "idive", |
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}; |
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static const char *clk_base_names[BASE_CLK_MAX] = { |
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[BASE_SAFE_CLK] = "base_safe_clk", |
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[BASE_USB0_CLK] = "base_usb0_clk", |
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[BASE_PERIPH_CLK] = "base_periph_clk", |
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[BASE_USB1_CLK] = "base_usb1_clk", |
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[BASE_CPU_CLK] = "base_cpu_clk", |
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[BASE_SPIFI_CLK] = "base_spifi_clk", |
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[BASE_SPI_CLK] = "base_spi_clk", |
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[BASE_PHY_RX_CLK] = "base_phy_rx_clk", |
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[BASE_PHY_TX_CLK] = "base_phy_tx_clk", |
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[BASE_APB1_CLK] = "base_apb1_clk", |
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[BASE_APB3_CLK] = "base_apb3_clk", |
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[BASE_LCD_CLK] = "base_lcd_clk", |
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[BASE_ADCHS_CLK] = "base_adchs_clk", |
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[BASE_SDIO_CLK] = "base_sdio_clk", |
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[BASE_SSP0_CLK] = "base_ssp0_clk", |
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[BASE_SSP1_CLK] = "base_ssp1_clk", |
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[BASE_UART0_CLK] = "base_uart0_clk", |
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[BASE_UART1_CLK] = "base_uart1_clk", |
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[BASE_UART2_CLK] = "base_uart2_clk", |
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[BASE_UART3_CLK] = "base_uart3_clk", |
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[BASE_OUT_CLK] = "base_out_clk", |
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[BASE_AUDIO_CLK] = "base_audio_clk", |
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[BASE_CGU_OUT0_CLK] = "base_cgu_out0_clk", |
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[BASE_CGU_OUT1_CLK] = "base_cgu_out1_clk", |
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}; |
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static u32 lpc18xx_cgu_pll0_src_ids[] = { |
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CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK, |
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CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC, |
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CLK_SRC_PLL1, CLK_SRC_IDIVA, CLK_SRC_IDIVB, CLK_SRC_IDIVC, |
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CLK_SRC_IDIVD, CLK_SRC_IDIVE, |
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}; |
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static u32 lpc18xx_cgu_pll1_src_ids[] = { |
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CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK, |
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CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC, |
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CLK_SRC_PLL0USB, CLK_SRC_PLL0AUDIO, CLK_SRC_IDIVA, |
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CLK_SRC_IDIVB, CLK_SRC_IDIVC, CLK_SRC_IDIVD, CLK_SRC_IDIVE, |
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}; |
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static u32 lpc18xx_cgu_idiva_src_ids[] = { |
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CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK, |
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CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC, |
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CLK_SRC_PLL0USB, CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1 |
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}; |
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static u32 lpc18xx_cgu_idivbcde_src_ids[] = { |
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CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK, |
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CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC, |
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CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1, CLK_SRC_IDIVA, |
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}; |
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static u32 lpc18xx_cgu_base_irc_src_ids[] = {CLK_SRC_IRC}; |
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static u32 lpc18xx_cgu_base_usb0_src_ids[] = {CLK_SRC_PLL0USB}; |
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static u32 lpc18xx_cgu_base_common_src_ids[] = { |
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CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK, |
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CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC, |
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CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1, CLK_SRC_IDIVA, |
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CLK_SRC_IDIVB, CLK_SRC_IDIVC, CLK_SRC_IDIVD, CLK_SRC_IDIVE, |
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}; |
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static u32 lpc18xx_cgu_base_all_src_ids[] = { |
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CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK, |
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CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC, |
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CLK_SRC_PLL0USB, CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1, |
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CLK_SRC_IDIVA, CLK_SRC_IDIVB, CLK_SRC_IDIVC, |
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CLK_SRC_IDIVD, CLK_SRC_IDIVE, |
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}; |
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struct lpc18xx_cgu_src_clk_div { |
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u8 clk_id; |
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u8 n_parents; |
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struct clk_divider div; |
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struct clk_mux mux; |
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struct clk_gate gate; |
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}; |
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#define LPC1XX_CGU_SRC_CLK_DIV(_id, _width, _table) \ |
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{ \ |
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.clk_id = CLK_SRC_ ##_id, \ |
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.n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \ |
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.div = { \ |
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.shift = 2, \ |
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.width = _width, \ |
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}, \ |
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.mux = { \ |
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.mask = 0x1f, \ |
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.shift = 24, \ |
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.table = lpc18xx_cgu_ ##_table, \ |
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}, \ |
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.gate = { \ |
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.bit_idx = 0, \ |
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.flags = CLK_GATE_SET_TO_DISABLE, \ |
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}, \ |
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} |
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static struct lpc18xx_cgu_src_clk_div lpc18xx_cgu_src_clk_divs[] = { |
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LPC1XX_CGU_SRC_CLK_DIV(IDIVA, 2, idiva_src_ids), |
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LPC1XX_CGU_SRC_CLK_DIV(IDIVB, 4, idivbcde_src_ids), |
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LPC1XX_CGU_SRC_CLK_DIV(IDIVC, 4, idivbcde_src_ids), |
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LPC1XX_CGU_SRC_CLK_DIV(IDIVD, 4, idivbcde_src_ids), |
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LPC1XX_CGU_SRC_CLK_DIV(IDIVE, 8, idivbcde_src_ids), |
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}; |
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struct lpc18xx_cgu_base_clk { |
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u8 clk_id; |
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u8 n_parents; |
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struct clk_mux mux; |
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struct clk_gate gate; |
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}; |
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#define LPC1XX_CGU_BASE_CLK(_id, _table, _flags) \ |
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{ \ |
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.clk_id = BASE_ ##_id ##_CLK, \ |
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.n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \ |
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.mux = { \ |
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.mask = 0x1f, \ |
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.shift = 24, \ |
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.table = lpc18xx_cgu_ ##_table, \ |
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.flags = _flags, \ |
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}, \ |
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.gate = { \ |
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.bit_idx = 0, \ |
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.flags = CLK_GATE_SET_TO_DISABLE, \ |
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}, \ |
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} |
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static struct lpc18xx_cgu_base_clk lpc18xx_cgu_base_clks[] = { |
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LPC1XX_CGU_BASE_CLK(SAFE, base_irc_src_ids, CLK_MUX_READ_ONLY), |
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LPC1XX_CGU_BASE_CLK(USB0, base_usb0_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(PERIPH, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(USB1, base_all_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(CPU, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(SPIFI, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(SPI, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(PHY_RX, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(PHY_TX, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(APB1, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(APB3, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(LCD, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(ADCHS, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(SDIO, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(SSP0, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(SSP1, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(UART0, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(UART1, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(UART2, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(UART3, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(OUT, base_all_src_ids, 0), |
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{ /* 21 reserved */ }, |
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{ /* 22 reserved */ }, |
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{ /* 23 reserved */ }, |
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{ /* 24 reserved */ }, |
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LPC1XX_CGU_BASE_CLK(AUDIO, base_common_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(CGU_OUT0, base_all_src_ids, 0), |
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LPC1XX_CGU_BASE_CLK(CGU_OUT1, base_all_src_ids, 0), |
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}; |
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struct lpc18xx_pll { |
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struct clk_hw hw; |
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void __iomem *reg; |
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spinlock_t *lock; |
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u8 flags; |
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}; |
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#define to_lpc_pll(hw) container_of(hw, struct lpc18xx_pll, hw) |
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struct lpc18xx_cgu_pll_clk { |
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u8 clk_id; |
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u8 n_parents; |
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u8 reg_offset; |
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struct clk_mux mux; |
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struct clk_gate gate; |
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struct lpc18xx_pll pll; |
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const struct clk_ops *pll_ops; |
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}; |
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#define LPC1XX_CGU_CLK_PLL(_id, _table, _pll_ops) \ |
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{ \ |
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.clk_id = CLK_SRC_ ##_id, \ |
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.n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \ |
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.reg_offset = LPC18XX_CGU_ ##_id ##_STAT, \ |
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.mux = { \ |
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.mask = 0x1f, \ |
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.shift = 24, \ |
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.table = lpc18xx_cgu_ ##_table, \ |
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}, \ |
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.gate = { \ |
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.bit_idx = 0, \ |
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.flags = CLK_GATE_SET_TO_DISABLE, \ |
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}, \ |
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.pll_ops = &lpc18xx_ ##_pll_ops, \ |
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} |
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/* |
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* PLL0 uses a special register value encoding. The compute functions below |
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* are taken or derived from the LPC1850 user manual (section 12.6.3.3). |
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*/ |
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/* Compute PLL0 multiplier from decoded version */ |
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static u32 lpc18xx_pll0_mdec2msel(u32 x) |
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{ |
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int i; |
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switch (x) { |
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case 0x18003: return 1; |
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case 0x10003: return 2; |
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default: |
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for (i = LPC18XX_PLL0_MSEL_MAX + 1; x != 0x4000 && i > 0; i--) |
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x = ((x ^ x >> 14) & 1) | (x << 1 & 0x7fff); |
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return i; |
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} |
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} |
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/* Compute PLL0 decoded multiplier from binary version */ |
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static u32 lpc18xx_pll0_msel2mdec(u32 msel) |
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{ |
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u32 i, x = 0x4000; |
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switch (msel) { |
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case 0: return 0; |
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case 1: return 0x18003; |
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case 2: return 0x10003; |
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default: |
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for (i = msel; i <= LPC18XX_PLL0_MSEL_MAX; i++) |
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x = ((x ^ x >> 1) & 1) << 14 | (x >> 1 & 0xffff); |
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return x; |
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} |
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} |
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/* Compute PLL0 bandwidth SELI reg from multiplier */ |
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static u32 lpc18xx_pll0_msel2seli(u32 msel) |
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{ |
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u32 tmp; |
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if (msel > 16384) return 1; |
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if (msel > 8192) return 2; |
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if (msel > 2048) return 4; |
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if (msel >= 501) return 8; |
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if (msel >= 60) { |
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tmp = 1024 / (msel + 9); |
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return ((1024 == (tmp * (msel + 9))) == 0) ? tmp * 4 : (tmp + 1) * 4; |
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} |
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return (msel & 0x3c) + 4; |
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} |
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/* Compute PLL0 bandwidth SELP reg from multiplier */ |
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static u32 lpc18xx_pll0_msel2selp(u32 msel) |
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{ |
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if (msel < 60) |
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return (msel >> 1) + 1; |
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return 31; |
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} |
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static unsigned long lpc18xx_pll0_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct lpc18xx_pll *pll = to_lpc_pll(hw); |
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u32 ctrl, mdiv, msel, npdiv; |
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ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); |
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mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV); |
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npdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); |
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if (ctrl & LPC18XX_PLL0_CTRL_BYPASS) |
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return parent_rate; |
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if (npdiv != LPC18XX_PLL0_NP_DIVS_1) { |
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pr_warn("%s: pre/post dividers not supported\n", __func__); |
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return 0; |
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} |
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msel = lpc18xx_pll0_mdec2msel(mdiv & LPC18XX_PLL0_MDIV_MDEC_MASK); |
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if (msel) |
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return 2 * msel * parent_rate; |
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pr_warn("%s: unable to calculate rate\n", __func__); |
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return 0; |
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} |
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static long lpc18xx_pll0_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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unsigned long m; |
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if (*prate < rate) { |
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pr_warn("%s: pll dividers not supported\n", __func__); |
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return -EINVAL; |
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} |
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m = DIV_ROUND_UP_ULL(*prate, rate * 2); |
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if (m <= 0 && m > LPC18XX_PLL0_MSEL_MAX) { |
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pr_warn("%s: unable to support rate %lu\n", __func__, rate); |
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return -EINVAL; |
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} |
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return 2 * *prate * m; |
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} |
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static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct lpc18xx_pll *pll = to_lpc_pll(hw); |
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u32 ctrl, stat, m; |
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int retry = 3; |
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if (parent_rate < rate) { |
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pr_warn("%s: pll dividers not supported\n", __func__); |
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return -EINVAL; |
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} |
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m = DIV_ROUND_UP_ULL(parent_rate, rate * 2); |
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if (m <= 0 && m > LPC18XX_PLL0_MSEL_MAX) { |
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pr_warn("%s: unable to support rate %lu\n", __func__, rate); |
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return -EINVAL; |
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} |
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m = lpc18xx_pll0_msel2mdec(m); |
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m |= lpc18xx_pll0_msel2selp(m) << LPC18XX_PLL0_MDIV_SELP_SHIFT; |
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m |= lpc18xx_pll0_msel2seli(m) << LPC18XX_PLL0_MDIV_SELI_SHIFT; |
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/* Power down PLL, disable clk output and dividers */ |
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ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL); |
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ctrl |= LPC18XX_PLL0_CTRL_PD; |
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ctrl &= ~(LPC18XX_PLL0_CTRL_BYPASS | LPC18XX_PLL0_CTRL_DIRECTI | |
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LPC18XX_PLL0_CTRL_DIRECTO | LPC18XX_PLL0_CTRL_CLKEN); |
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writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); |
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/* Configure new PLL settings */ |
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writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV); |
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writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV); |
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/* Power up PLL and wait for lock */ |
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ctrl &= ~LPC18XX_PLL0_CTRL_PD; |
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writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); |
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do { |
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udelay(10); |
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stat = readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT); |
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if (stat & LPC18XX_PLL0_STAT_LOCK) { |
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ctrl |= LPC18XX_PLL0_CTRL_CLKEN; |
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writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL); |
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return 0; |
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} |
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} while (retry--); |
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pr_warn("%s: unable to lock pll\n", __func__); |
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|
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return -EINVAL; |
|
} |
|
|
|
static const struct clk_ops lpc18xx_pll0_ops = { |
|
.recalc_rate = lpc18xx_pll0_recalc_rate, |
|
.round_rate = lpc18xx_pll0_round_rate, |
|
.set_rate = lpc18xx_pll0_set_rate, |
|
}; |
|
|
|
static unsigned long lpc18xx_pll1_recalc_rate(struct clk_hw *hw, |
|
unsigned long parent_rate) |
|
{ |
|
struct lpc18xx_pll *pll = to_lpc_pll(hw); |
|
u16 msel, nsel, psel; |
|
bool direct, fbsel; |
|
u32 stat, ctrl; |
|
|
|
stat = readl(pll->reg + LPC18XX_CGU_PLL1_STAT); |
|
ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL); |
|
|
|
direct = (ctrl & LPC18XX_PLL1_CTRL_DIRECT) ? true : false; |
|
fbsel = (ctrl & LPC18XX_PLL1_CTRL_FBSEL) ? true : false; |
|
|
|
msel = ((ctrl >> 16) & 0xff) + 1; |
|
nsel = ((ctrl >> 12) & 0x3) + 1; |
|
|
|
if (direct || fbsel) |
|
return msel * (parent_rate / nsel); |
|
|
|
psel = (ctrl >> 8) & 0x3; |
|
psel = 1 << psel; |
|
|
|
return (msel / (2 * psel)) * (parent_rate / nsel); |
|
} |
|
|
|
static const struct clk_ops lpc18xx_pll1_ops = { |
|
.recalc_rate = lpc18xx_pll1_recalc_rate, |
|
}; |
|
|
|
static int lpc18xx_cgu_gate_enable(struct clk_hw *hw) |
|
{ |
|
return clk_gate_ops.enable(hw); |
|
} |
|
|
|
static void lpc18xx_cgu_gate_disable(struct clk_hw *hw) |
|
{ |
|
clk_gate_ops.disable(hw); |
|
} |
|
|
|
static int lpc18xx_cgu_gate_is_enabled(struct clk_hw *hw) |
|
{ |
|
const struct clk_hw *parent; |
|
|
|
/* |
|
* The consumer of base clocks needs know if the |
|
* base clock is really enabled before it can be |
|
* accessed. It is therefore necessary to verify |
|
* this all the way up. |
|
*/ |
|
parent = clk_hw_get_parent(hw); |
|
if (!parent) |
|
return 0; |
|
|
|
if (!clk_hw_is_enabled(parent)) |
|
return 0; |
|
|
|
return clk_gate_ops.is_enabled(hw); |
|
} |
|
|
|
static const struct clk_ops lpc18xx_gate_ops = { |
|
.enable = lpc18xx_cgu_gate_enable, |
|
.disable = lpc18xx_cgu_gate_disable, |
|
.is_enabled = lpc18xx_cgu_gate_is_enabled, |
|
}; |
|
|
|
static struct lpc18xx_cgu_pll_clk lpc18xx_cgu_src_clk_plls[] = { |
|
LPC1XX_CGU_CLK_PLL(PLL0USB, pll0_src_ids, pll0_ops), |
|
LPC1XX_CGU_CLK_PLL(PLL0AUDIO, pll0_src_ids, pll0_ops), |
|
LPC1XX_CGU_CLK_PLL(PLL1, pll1_src_ids, pll1_ops), |
|
}; |
|
|
|
static void lpc18xx_fill_parent_names(const char **parent, u32 *id, int size) |
|
{ |
|
int i; |
|
|
|
for (i = 0; i < size; i++) |
|
parent[i] = clk_src_names[id[i]]; |
|
} |
|
|
|
static struct clk *lpc18xx_cgu_register_div(struct lpc18xx_cgu_src_clk_div *clk, |
|
void __iomem *base, int n) |
|
{ |
|
void __iomem *reg = base + LPC18XX_CGU_IDIV_CTRL(n); |
|
const char *name = clk_src_names[clk->clk_id]; |
|
const char *parents[CLK_SRC_MAX]; |
|
|
|
clk->div.reg = reg; |
|
clk->mux.reg = reg; |
|
clk->gate.reg = reg; |
|
|
|
lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); |
|
|
|
return clk_register_composite(NULL, name, parents, clk->n_parents, |
|
&clk->mux.hw, &clk_mux_ops, |
|
&clk->div.hw, &clk_divider_ops, |
|
&clk->gate.hw, &lpc18xx_gate_ops, 0); |
|
} |
|
|
|
|
|
static struct clk *lpc18xx_register_base_clk(struct lpc18xx_cgu_base_clk *clk, |
|
void __iomem *reg_base, int n) |
|
{ |
|
void __iomem *reg = reg_base + LPC18XX_CGU_BASE_CLK(n); |
|
const char *name = clk_base_names[clk->clk_id]; |
|
const char *parents[CLK_SRC_MAX]; |
|
|
|
if (clk->n_parents == 0) |
|
return ERR_PTR(-ENOENT); |
|
|
|
clk->mux.reg = reg; |
|
clk->gate.reg = reg; |
|
|
|
lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); |
|
|
|
/* SAFE_CLK can not be turned off */ |
|
if (n == BASE_SAFE_CLK) |
|
return clk_register_composite(NULL, name, parents, clk->n_parents, |
|
&clk->mux.hw, &clk_mux_ops, |
|
NULL, NULL, NULL, NULL, 0); |
|
|
|
return clk_register_composite(NULL, name, parents, clk->n_parents, |
|
&clk->mux.hw, &clk_mux_ops, |
|
NULL, NULL, |
|
&clk->gate.hw, &lpc18xx_gate_ops, 0); |
|
} |
|
|
|
|
|
static struct clk *lpc18xx_cgu_register_pll(struct lpc18xx_cgu_pll_clk *clk, |
|
void __iomem *base) |
|
{ |
|
const char *name = clk_src_names[clk->clk_id]; |
|
const char *parents[CLK_SRC_MAX]; |
|
|
|
clk->pll.reg = base; |
|
clk->mux.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET; |
|
clk->gate.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET; |
|
|
|
lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); |
|
|
|
return clk_register_composite(NULL, name, parents, clk->n_parents, |
|
&clk->mux.hw, &clk_mux_ops, |
|
&clk->pll.hw, clk->pll_ops, |
|
&clk->gate.hw, &lpc18xx_gate_ops, 0); |
|
} |
|
|
|
static void __init lpc18xx_cgu_register_source_clks(struct device_node *np, |
|
void __iomem *base) |
|
{ |
|
const char *parents[CLK_SRC_MAX]; |
|
struct clk *clk; |
|
int i; |
|
|
|
/* Register the internal 12 MHz RC oscillator (IRC) */ |
|
clk = clk_register_fixed_rate(NULL, clk_src_names[CLK_SRC_IRC], |
|
NULL, 0, 12000000); |
|
if (IS_ERR(clk)) |
|
pr_warn("%s: failed to register irc clk\n", __func__); |
|
|
|
/* Register crystal oscillator controlller */ |
|
parents[0] = of_clk_get_parent_name(np, 0); |
|
clk = clk_register_gate(NULL, clk_src_names[CLK_SRC_OSC], parents[0], |
|
0, base + LPC18XX_CGU_XTAL_OSC_CTRL, |
|
0, CLK_GATE_SET_TO_DISABLE, NULL); |
|
if (IS_ERR(clk)) |
|
pr_warn("%s: failed to register osc clk\n", __func__); |
|
|
|
/* Register all PLLs */ |
|
for (i = 0; i < ARRAY_SIZE(lpc18xx_cgu_src_clk_plls); i++) { |
|
clk = lpc18xx_cgu_register_pll(&lpc18xx_cgu_src_clk_plls[i], |
|
base); |
|
if (IS_ERR(clk)) |
|
pr_warn("%s: failed to register pll (%d)\n", __func__, i); |
|
} |
|
|
|
/* Register all clock dividers A-E */ |
|
for (i = 0; i < ARRAY_SIZE(lpc18xx_cgu_src_clk_divs); i++) { |
|
clk = lpc18xx_cgu_register_div(&lpc18xx_cgu_src_clk_divs[i], |
|
base, i); |
|
if (IS_ERR(clk)) |
|
pr_warn("%s: failed to register div %d\n", __func__, i); |
|
} |
|
} |
|
|
|
static struct clk *clk_base[BASE_CLK_MAX]; |
|
static struct clk_onecell_data clk_base_data = { |
|
.clks = clk_base, |
|
.clk_num = BASE_CLK_MAX, |
|
}; |
|
|
|
static void __init lpc18xx_cgu_register_base_clks(void __iomem *reg_base) |
|
{ |
|
int i; |
|
|
|
for (i = BASE_SAFE_CLK; i < BASE_CLK_MAX; i++) { |
|
clk_base[i] = lpc18xx_register_base_clk(&lpc18xx_cgu_base_clks[i], |
|
reg_base, i); |
|
if (IS_ERR(clk_base[i]) && PTR_ERR(clk_base[i]) != -ENOENT) |
|
pr_warn("%s: register base clk %d failed\n", __func__, i); |
|
} |
|
} |
|
|
|
static void __init lpc18xx_cgu_init(struct device_node *np) |
|
{ |
|
void __iomem *reg_base; |
|
|
|
reg_base = of_iomap(np, 0); |
|
if (!reg_base) { |
|
pr_warn("%s: failed to map address range\n", __func__); |
|
return; |
|
} |
|
|
|
lpc18xx_cgu_register_source_clks(np, reg_base); |
|
lpc18xx_cgu_register_base_clks(reg_base); |
|
|
|
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_base_data); |
|
} |
|
CLK_OF_DECLARE(lpc18xx_cgu, "nxp,lpc1850-cgu", lpc18xx_cgu_init);
|
|
|