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358 lines
8.4 KiB
358 lines
8.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Marvell Kirkwood SoC clocks |
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* |
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* Copyright (C) 2012 Marvell |
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* |
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* Gregory CLEMENT <[email protected]> |
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* Sebastian Hesselbarth <[email protected]> |
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* Andrew Lunn <[email protected]> |
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* |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/slab.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include "common.h" |
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/* |
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* Core Clocks |
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* |
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* Kirkwood PLL sample-at-reset configuration |
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* (6180 has different SAR layout than other Kirkwood SoCs) |
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* |
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* SAR0[4:3,22,1] : CPU frequency (6281,6292,6282) |
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* 4 = 600 MHz |
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* 6 = 800 MHz |
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* 7 = 1000 MHz |
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* 9 = 1200 MHz |
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* 12 = 1500 MHz |
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* 13 = 1600 MHz |
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* 14 = 1800 MHz |
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* 15 = 2000 MHz |
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* others reserved. |
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* |
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* SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282) |
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* 1 = (1/2) * CPU |
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* 3 = (1/3) * CPU |
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* 5 = (1/4) * CPU |
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* others reserved. |
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* |
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* SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282) |
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* 2 = (1/2) * CPU |
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* 4 = (1/3) * CPU |
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* 6 = (1/4) * CPU |
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* 7 = (2/9) * CPU |
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* 8 = (1/5) * CPU |
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* 9 = (1/6) * CPU |
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* others reserved. |
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* |
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* SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only) |
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* 5 = [CPU = 600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU] |
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* 6 = [CPU = 800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU] |
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* 7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU] |
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* others reserved. |
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* |
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* SAR0[21] : TCLK frequency |
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* 0 = 200 MHz |
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* 1 = 166 MHz |
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* others reserved. |
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*/ |
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#define SAR_KIRKWOOD_CPU_FREQ(x) \ |
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(((x & (1 << 1)) >> 1) | \ |
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((x & (1 << 22)) >> 21) | \ |
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((x & (3 << 3)) >> 1)) |
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#define SAR_KIRKWOOD_L2_RATIO(x) \ |
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(((x & (3 << 9)) >> 9) | \ |
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(((x & (1 << 19)) >> 17))) |
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#define SAR_KIRKWOOD_DDR_RATIO 5 |
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#define SAR_KIRKWOOD_DDR_RATIO_MASK 0xf |
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#define SAR_MV88F6180_CLK 2 |
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#define SAR_MV88F6180_CLK_MASK 0x7 |
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#define SAR_KIRKWOOD_TCLK_FREQ 21 |
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#define SAR_KIRKWOOD_TCLK_FREQ_MASK 0x1 |
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enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR }; |
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static const struct coreclk_ratio kirkwood_coreclk_ratios[] __initconst = { |
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{ .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", }, |
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{ .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", } |
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}; |
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static u32 __init kirkwood_get_tclk_freq(void __iomem *sar) |
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{ |
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u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) & |
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SAR_KIRKWOOD_TCLK_FREQ_MASK; |
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return (opt) ? 166666667 : 200000000; |
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} |
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static const u32 kirkwood_cpu_freqs[] __initconst = { |
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0, 0, 0, 0, |
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600000000, |
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0, |
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800000000, |
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1000000000, |
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0, |
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1200000000, |
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0, 0, |
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1500000000, |
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1600000000, |
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1800000000, |
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2000000000 |
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}; |
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static u32 __init kirkwood_get_cpu_freq(void __iomem *sar) |
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{ |
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u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar)); |
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return kirkwood_cpu_freqs[opt]; |
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} |
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static const int kirkwood_cpu_l2_ratios[8][2] __initconst = { |
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{ 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 }, |
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{ 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 } |
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}; |
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static const int kirkwood_cpu_ddr_ratios[16][2] __initconst = { |
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{ 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 }, |
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{ 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 }, |
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{ 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 }, |
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{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } |
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}; |
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static void __init kirkwood_get_clk_ratio( |
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void __iomem *sar, int id, int *mult, int *div) |
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{ |
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switch (id) { |
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case KIRKWOOD_CPU_TO_L2: |
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{ |
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u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar)); |
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*mult = kirkwood_cpu_l2_ratios[opt][0]; |
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*div = kirkwood_cpu_l2_ratios[opt][1]; |
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break; |
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} |
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case KIRKWOOD_CPU_TO_DDR: |
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{ |
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u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) & |
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SAR_KIRKWOOD_DDR_RATIO_MASK; |
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*mult = kirkwood_cpu_ddr_ratios[opt][0]; |
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*div = kirkwood_cpu_ddr_ratios[opt][1]; |
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break; |
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} |
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} |
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} |
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static const u32 mv88f6180_cpu_freqs[] __initconst = { |
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0, 0, 0, 0, 0, |
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600000000, |
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800000000, |
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1000000000 |
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}; |
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static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar) |
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{ |
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u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK; |
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return mv88f6180_cpu_freqs[opt]; |
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} |
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static const int mv88f6180_cpu_ddr_ratios[8][2] __initconst = { |
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{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, |
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{ 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 } |
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}; |
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static void __init mv88f6180_get_clk_ratio( |
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void __iomem *sar, int id, int *mult, int *div) |
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{ |
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switch (id) { |
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case KIRKWOOD_CPU_TO_L2: |
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{ |
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/* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */ |
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*mult = 1; |
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*div = 2; |
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break; |
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} |
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case KIRKWOOD_CPU_TO_DDR: |
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{ |
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u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & |
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SAR_MV88F6180_CLK_MASK; |
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*mult = mv88f6180_cpu_ddr_ratios[opt][0]; |
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*div = mv88f6180_cpu_ddr_ratios[opt][1]; |
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break; |
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} |
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} |
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} |
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static u32 __init mv98dx1135_get_tclk_freq(void __iomem *sar) |
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{ |
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return 166666667; |
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} |
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static const struct coreclk_soc_desc kirkwood_coreclks = { |
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.get_tclk_freq = kirkwood_get_tclk_freq, |
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.get_cpu_freq = kirkwood_get_cpu_freq, |
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.get_clk_ratio = kirkwood_get_clk_ratio, |
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.ratios = kirkwood_coreclk_ratios, |
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.num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios), |
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}; |
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static const struct coreclk_soc_desc mv88f6180_coreclks = { |
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.get_tclk_freq = kirkwood_get_tclk_freq, |
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.get_cpu_freq = mv88f6180_get_cpu_freq, |
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.get_clk_ratio = mv88f6180_get_clk_ratio, |
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.ratios = kirkwood_coreclk_ratios, |
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.num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios), |
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}; |
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static const struct coreclk_soc_desc mv98dx1135_coreclks = { |
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.get_tclk_freq = mv98dx1135_get_tclk_freq, |
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.get_cpu_freq = kirkwood_get_cpu_freq, |
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.get_clk_ratio = kirkwood_get_clk_ratio, |
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.ratios = kirkwood_coreclk_ratios, |
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.num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios), |
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}; |
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/* |
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* Clock Gating Control |
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*/ |
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static const struct clk_gating_soc_desc kirkwood_gating_desc[] __initconst = { |
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{ "ge0", NULL, 0, 0 }, |
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{ "pex0", NULL, 2, 0 }, |
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{ "usb0", NULL, 3, 0 }, |
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{ "sdio", NULL, 4, 0 }, |
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{ "tsu", NULL, 5, 0 }, |
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{ "runit", NULL, 7, 0 }, |
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{ "xor0", NULL, 8, 0 }, |
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{ "audio", NULL, 9, 0 }, |
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{ "sata0", NULL, 14, 0 }, |
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{ "sata1", NULL, 15, 0 }, |
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{ "xor1", NULL, 16, 0 }, |
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{ "crypto", NULL, 17, 0 }, |
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{ "pex1", NULL, 18, 0 }, |
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{ "ge1", NULL, 19, 0 }, |
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{ "tdm", NULL, 20, 0 }, |
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{ } |
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}; |
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/* |
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* Clock Muxing Control |
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*/ |
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struct clk_muxing_soc_desc { |
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const char *name; |
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const char **parents; |
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int num_parents; |
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int shift; |
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int width; |
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unsigned long flags; |
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}; |
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struct clk_muxing_ctrl { |
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spinlock_t *lock; |
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struct clk **muxes; |
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int num_muxes; |
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}; |
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static const char *powersave_parents[] = { |
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"cpuclk", |
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"ddrclk", |
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}; |
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static const struct clk_muxing_soc_desc kirkwood_mux_desc[] __initconst = { |
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{ "powersave", powersave_parents, ARRAY_SIZE(powersave_parents), |
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11, 1, 0 }, |
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}; |
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static struct clk *clk_muxing_get_src( |
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struct of_phandle_args *clkspec, void *data) |
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{ |
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struct clk_muxing_ctrl *ctrl = (struct clk_muxing_ctrl *)data; |
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int n; |
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if (clkspec->args_count < 1) |
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return ERR_PTR(-EINVAL); |
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for (n = 0; n < ctrl->num_muxes; n++) { |
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struct clk_mux *mux = |
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to_clk_mux(__clk_get_hw(ctrl->muxes[n])); |
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if (clkspec->args[0] == mux->shift) |
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return ctrl->muxes[n]; |
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} |
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return ERR_PTR(-ENODEV); |
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} |
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static void __init kirkwood_clk_muxing_setup(struct device_node *np, |
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const struct clk_muxing_soc_desc *desc) |
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{ |
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struct clk_muxing_ctrl *ctrl; |
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void __iomem *base; |
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int n; |
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base = of_iomap(np, 0); |
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if (WARN_ON(!base)) |
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return; |
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ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
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if (WARN_ON(!ctrl)) |
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goto ctrl_out; |
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/* lock must already be initialized */ |
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ctrl->lock = &ctrl_gating_lock; |
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/* Count, allocate, and register clock muxes */ |
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for (n = 0; desc[n].name;) |
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n++; |
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ctrl->num_muxes = n; |
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ctrl->muxes = kcalloc(ctrl->num_muxes, sizeof(struct clk *), |
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GFP_KERNEL); |
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if (WARN_ON(!ctrl->muxes)) |
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goto muxes_out; |
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for (n = 0; n < ctrl->num_muxes; n++) { |
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ctrl->muxes[n] = clk_register_mux(NULL, desc[n].name, |
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desc[n].parents, desc[n].num_parents, |
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desc[n].flags, base, desc[n].shift, |
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desc[n].width, desc[n].flags, ctrl->lock); |
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WARN_ON(IS_ERR(ctrl->muxes[n])); |
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} |
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of_clk_add_provider(np, clk_muxing_get_src, ctrl); |
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return; |
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muxes_out: |
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kfree(ctrl); |
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ctrl_out: |
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iounmap(base); |
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} |
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static void __init kirkwood_clk_init(struct device_node *np) |
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{ |
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struct device_node *cgnp = |
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of_find_compatible_node(NULL, NULL, "marvell,kirkwood-gating-clock"); |
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if (of_device_is_compatible(np, "marvell,mv88f6180-core-clock")) |
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mvebu_coreclk_setup(np, &mv88f6180_coreclks); |
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else if (of_device_is_compatible(np, "marvell,mv98dx1135-core-clock")) |
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mvebu_coreclk_setup(np, &mv98dx1135_coreclks); |
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else |
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mvebu_coreclk_setup(np, &kirkwood_coreclks); |
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if (cgnp) { |
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mvebu_clk_gating_setup(cgnp, kirkwood_gating_desc); |
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kirkwood_clk_muxing_setup(cgnp, kirkwood_mux_desc); |
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of_node_put(cgnp); |
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} |
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} |
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CLK_OF_DECLARE(kirkwood_clk, "marvell,kirkwood-core-clock", |
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kirkwood_clk_init); |
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CLK_OF_DECLARE(mv88f6180_clk, "marvell,mv88f6180-core-clock", |
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kirkwood_clk_init); |
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CLK_OF_DECLARE(98dx1135_clk, "marvell,mv98dx1135-core-clock", |
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kirkwood_clk_init);
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