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262 lines
5.7 KiB
262 lines
5.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Marvell Dove PMU Core PLL divider driver |
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* |
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* Cleaned up by substantially rewriting, and converted to DT by |
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* Russell King. Origin is not known. |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include "dove-divider.h" |
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struct dove_clk { |
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const char *name; |
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struct clk_hw hw; |
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void __iomem *base; |
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spinlock_t *lock; |
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u8 div_bit_start; |
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u8 div_bit_end; |
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u8 div_bit_load; |
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u8 div_bit_size; |
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u32 *divider_table; |
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}; |
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enum { |
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DIV_CTRL0 = 0, |
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DIV_CTRL1 = 4, |
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DIV_CTRL1_N_RESET_MASK = BIT(10), |
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}; |
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#define to_dove_clk(hw) container_of(hw, struct dove_clk, hw) |
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static void dove_load_divider(void __iomem *base, u32 val, u32 mask, u32 load) |
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{ |
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u32 v; |
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v = readl_relaxed(base + DIV_CTRL1) | DIV_CTRL1_N_RESET_MASK; |
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writel_relaxed(v, base + DIV_CTRL1); |
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v = (readl_relaxed(base + DIV_CTRL0) & ~(mask | load)) | val; |
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writel_relaxed(v, base + DIV_CTRL0); |
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writel_relaxed(v | load, base + DIV_CTRL0); |
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ndelay(250); |
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writel_relaxed(v, base + DIV_CTRL0); |
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} |
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static unsigned int dove_get_divider(struct dove_clk *dc) |
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{ |
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unsigned int divider; |
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u32 val; |
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val = readl_relaxed(dc->base + DIV_CTRL0); |
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val >>= dc->div_bit_start; |
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divider = val & ~(~0 << dc->div_bit_size); |
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if (dc->divider_table) |
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divider = dc->divider_table[divider]; |
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return divider; |
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} |
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static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, |
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unsigned long parent_rate, bool set) |
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{ |
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unsigned int divider, max; |
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divider = DIV_ROUND_CLOSEST(parent_rate, rate); |
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if (dc->divider_table) { |
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unsigned int i; |
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for (i = 0; dc->divider_table[i]; i++) |
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if (divider == dc->divider_table[i]) { |
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divider = i; |
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break; |
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} |
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if (!dc->divider_table[i]) |
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return -EINVAL; |
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} else { |
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max = 1 << dc->div_bit_size; |
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if (set && (divider == 0 || divider >= max)) |
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return -EINVAL; |
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if (divider >= max) |
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divider = max - 1; |
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else if (divider == 0) |
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divider = 1; |
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} |
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return divider; |
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} |
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static unsigned long dove_recalc_rate(struct clk_hw *hw, unsigned long parent) |
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{ |
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struct dove_clk *dc = to_dove_clk(hw); |
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unsigned int divider = dove_get_divider(dc); |
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unsigned long rate = DIV_ROUND_CLOSEST(parent, divider); |
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pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n", |
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__func__, dc->name, divider, parent, rate); |
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return rate; |
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} |
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static long dove_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *parent) |
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{ |
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struct dove_clk *dc = to_dove_clk(hw); |
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unsigned long parent_rate = *parent; |
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int divider; |
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divider = dove_calc_divider(dc, rate, parent_rate, false); |
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if (divider < 0) |
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return divider; |
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rate = DIV_ROUND_CLOSEST(parent_rate, divider); |
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pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n", |
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__func__, dc->name, divider, parent_rate, rate); |
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return rate; |
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} |
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static int dove_set_clock(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct dove_clk *dc = to_dove_clk(hw); |
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u32 mask, load, div; |
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int divider; |
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divider = dove_calc_divider(dc, rate, parent_rate, true); |
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if (divider < 0) |
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return divider; |
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pr_debug("%s(): %s divider=%u parent=%lu rate=%lu\n", |
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__func__, dc->name, divider, parent_rate, rate); |
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div = (u32)divider << dc->div_bit_start; |
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mask = ~(~0 << dc->div_bit_size) << dc->div_bit_start; |
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load = BIT(dc->div_bit_load); |
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spin_lock(dc->lock); |
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dove_load_divider(dc->base, div, mask, load); |
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spin_unlock(dc->lock); |
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return 0; |
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} |
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static const struct clk_ops dove_divider_ops = { |
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.set_rate = dove_set_clock, |
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.round_rate = dove_round_rate, |
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.recalc_rate = dove_recalc_rate, |
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}; |
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static struct clk *clk_register_dove_divider(struct device *dev, |
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struct dove_clk *dc, const char **parent_names, size_t num_parents, |
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void __iomem *base) |
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{ |
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char name[32]; |
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struct clk_init_data init = { |
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.name = name, |
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.ops = &dove_divider_ops, |
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.parent_names = parent_names, |
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.num_parents = num_parents, |
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}; |
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strlcpy(name, dc->name, sizeof(name)); |
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dc->hw.init = &init; |
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dc->base = base; |
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dc->div_bit_size = dc->div_bit_end - dc->div_bit_start + 1; |
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return clk_register(dev, &dc->hw); |
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} |
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static DEFINE_SPINLOCK(dove_divider_lock); |
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static u32 axi_divider[] = {-1, 2, 1, 3, 4, 6, 5, 7, 8, 10, 9, 0}; |
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static struct dove_clk dove_hw_clocks[4] = { |
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{ |
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.name = "axi", |
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.lock = &dove_divider_lock, |
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.div_bit_start = 1, |
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.div_bit_end = 6, |
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.div_bit_load = 7, |
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.divider_table = axi_divider, |
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}, { |
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.name = "gpu", |
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.lock = &dove_divider_lock, |
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.div_bit_start = 8, |
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.div_bit_end = 13, |
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.div_bit_load = 14, |
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}, { |
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.name = "vmeta", |
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.lock = &dove_divider_lock, |
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.div_bit_start = 15, |
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.div_bit_end = 20, |
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.div_bit_load = 21, |
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}, { |
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.name = "lcd", |
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.lock = &dove_divider_lock, |
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.div_bit_start = 22, |
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.div_bit_end = 27, |
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.div_bit_load = 28, |
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}, |
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}; |
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static const char *core_pll[] = { |
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"core-pll", |
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}; |
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static int dove_divider_init(struct device *dev, void __iomem *base, |
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struct clk **clks) |
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{ |
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struct clk *clk; |
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int i; |
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/* |
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* Create the core PLL clock. We treat this as a fixed rate |
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* clock as we don't know any better, and documentation is sparse. |
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*/ |
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clk = clk_register_fixed_rate(dev, core_pll[0], NULL, 0, 2000000000UL); |
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if (IS_ERR(clk)) |
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return PTR_ERR(clk); |
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for (i = 0; i < ARRAY_SIZE(dove_hw_clocks); i++) |
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clks[i] = clk_register_dove_divider(dev, &dove_hw_clocks[i], |
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core_pll, |
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ARRAY_SIZE(core_pll), base); |
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return 0; |
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} |
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static struct clk *dove_divider_clocks[4]; |
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static struct clk_onecell_data dove_divider_data = { |
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.clks = dove_divider_clocks, |
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.clk_num = ARRAY_SIZE(dove_divider_clocks), |
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}; |
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void __init dove_divider_clk_init(struct device_node *np) |
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{ |
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void __iomem *base; |
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base = of_iomap(np, 0); |
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if (WARN_ON(!base)) |
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return; |
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if (WARN_ON(dove_divider_init(NULL, base, dove_divider_clocks))) { |
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iounmap(base); |
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return; |
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} |
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of_clk_add_provider(np, of_clk_src_onecell_get, &dove_divider_data); |
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}
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