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434 lines
11 KiB
434 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Marvell Armada CP110 System Controller |
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* |
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* Copyright (C) 2016 Marvell |
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* |
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* Thomas Petazzoni <[email protected]> |
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* |
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*/ |
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/* |
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* CP110 has 6 core clocks: |
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* |
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* - PLL0 (1 Ghz) |
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* - PPv2 core (1/3 PLL0) |
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* - x2 Core (1/2 PLL0) |
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* - Core (1/2 x2 Core) |
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* - SDIO (2/5 PLL0) |
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* |
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* - NAND clock, which is either: |
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* - Equal to SDIO clock |
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* - 2/5 PLL0 |
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* |
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* CP110 has 32 gateable clocks, for the various peripherals in the IP. |
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*/ |
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#define pr_fmt(fmt) "cp110-system-controller: " fmt |
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#include "armada_ap_cp_helper.h" |
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#include <linux/clk-provider.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/init.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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#define CP110_PM_CLOCK_GATING_REG 0x220 |
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#define CP110_NAND_FLASH_CLK_CTRL_REG 0x700 |
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#define NF_CLOCK_SEL_400_MASK BIT(0) |
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enum { |
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CP110_CLK_TYPE_CORE, |
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CP110_CLK_TYPE_GATABLE, |
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}; |
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#define CP110_MAX_CORE_CLOCKS 6 |
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#define CP110_MAX_GATABLE_CLOCKS 32 |
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#define CP110_CLK_NUM \ |
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(CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS) |
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#define CP110_CORE_PLL0 0 |
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#define CP110_CORE_PPV2 1 |
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#define CP110_CORE_X2CORE 2 |
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#define CP110_CORE_CORE 3 |
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#define CP110_CORE_NAND 4 |
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#define CP110_CORE_SDIO 5 |
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/* A number of gateable clocks need special handling */ |
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#define CP110_GATE_AUDIO 0 |
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#define CP110_GATE_COMM_UNIT 1 |
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#define CP110_GATE_NAND 2 |
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#define CP110_GATE_PPV2 3 |
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#define CP110_GATE_SDIO 4 |
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#define CP110_GATE_MG 5 |
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#define CP110_GATE_MG_CORE 6 |
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#define CP110_GATE_XOR1 7 |
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#define CP110_GATE_XOR0 8 |
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#define CP110_GATE_GOP_DP 9 |
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#define CP110_GATE_PCIE_X1_0 11 |
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#define CP110_GATE_PCIE_X1_1 12 |
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#define CP110_GATE_PCIE_X4 13 |
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#define CP110_GATE_PCIE_XOR 14 |
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#define CP110_GATE_SATA 15 |
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#define CP110_GATE_SATA_USB 16 |
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#define CP110_GATE_MAIN 17 |
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#define CP110_GATE_SDMMC_GOP 18 |
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#define CP110_GATE_SLOW_IO 21 |
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#define CP110_GATE_USB3H0 22 |
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#define CP110_GATE_USB3H1 23 |
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#define CP110_GATE_USB3DEV 24 |
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#define CP110_GATE_EIP150 25 |
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#define CP110_GATE_EIP197 26 |
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static const char * const gate_base_names[] = { |
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[CP110_GATE_AUDIO] = "audio", |
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[CP110_GATE_COMM_UNIT] = "communit", |
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[CP110_GATE_NAND] = "nand", |
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[CP110_GATE_PPV2] = "ppv2", |
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[CP110_GATE_SDIO] = "sdio", |
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[CP110_GATE_MG] = "mg-domain", |
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[CP110_GATE_MG_CORE] = "mg-core", |
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[CP110_GATE_XOR1] = "xor1", |
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[CP110_GATE_XOR0] = "xor0", |
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[CP110_GATE_GOP_DP] = "gop-dp", |
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[CP110_GATE_PCIE_X1_0] = "pcie_x10", |
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[CP110_GATE_PCIE_X1_1] = "pcie_x11", |
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[CP110_GATE_PCIE_X4] = "pcie_x4", |
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[CP110_GATE_PCIE_XOR] = "pcie-xor", |
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[CP110_GATE_SATA] = "sata", |
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[CP110_GATE_SATA_USB] = "sata-usb", |
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[CP110_GATE_MAIN] = "main", |
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[CP110_GATE_SDMMC_GOP] = "sd-mmc-gop", |
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[CP110_GATE_SLOW_IO] = "slow-io", |
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[CP110_GATE_USB3H0] = "usb3h0", |
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[CP110_GATE_USB3H1] = "usb3h1", |
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[CP110_GATE_USB3DEV] = "usb3dev", |
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[CP110_GATE_EIP150] = "eip150", |
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[CP110_GATE_EIP197] = "eip197" |
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}; |
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struct cp110_gate_clk { |
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struct clk_hw hw; |
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struct regmap *regmap; |
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u8 bit_idx; |
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}; |
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#define to_cp110_gate_clk(hw) container_of(hw, struct cp110_gate_clk, hw) |
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static int cp110_gate_enable(struct clk_hw *hw) |
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{ |
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struct cp110_gate_clk *gate = to_cp110_gate_clk(hw); |
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regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG, |
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BIT(gate->bit_idx), BIT(gate->bit_idx)); |
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return 0; |
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} |
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static void cp110_gate_disable(struct clk_hw *hw) |
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{ |
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struct cp110_gate_clk *gate = to_cp110_gate_clk(hw); |
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regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG, |
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BIT(gate->bit_idx), 0); |
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} |
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static int cp110_gate_is_enabled(struct clk_hw *hw) |
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{ |
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struct cp110_gate_clk *gate = to_cp110_gate_clk(hw); |
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u32 val; |
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regmap_read(gate->regmap, CP110_PM_CLOCK_GATING_REG, &val); |
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return val & BIT(gate->bit_idx); |
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} |
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static const struct clk_ops cp110_gate_ops = { |
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.enable = cp110_gate_enable, |
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.disable = cp110_gate_disable, |
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.is_enabled = cp110_gate_is_enabled, |
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}; |
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static struct clk_hw *cp110_register_gate(const char *name, |
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const char *parent_name, |
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struct regmap *regmap, u8 bit_idx) |
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{ |
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struct cp110_gate_clk *gate; |
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struct clk_hw *hw; |
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struct clk_init_data init; |
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int ret; |
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gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
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if (!gate) |
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return ERR_PTR(-ENOMEM); |
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memset(&init, 0, sizeof(init)); |
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init.name = name; |
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init.ops = &cp110_gate_ops; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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gate->regmap = regmap; |
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gate->bit_idx = bit_idx; |
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gate->hw.init = &init; |
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hw = &gate->hw; |
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ret = clk_hw_register(NULL, hw); |
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if (ret) { |
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kfree(gate); |
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hw = ERR_PTR(ret); |
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} |
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return hw; |
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} |
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static void cp110_unregister_gate(struct clk_hw *hw) |
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{ |
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clk_hw_unregister(hw); |
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kfree(to_cp110_gate_clk(hw)); |
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} |
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static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec, |
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void *data) |
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{ |
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struct clk_hw_onecell_data *clk_data = data; |
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unsigned int type = clkspec->args[0]; |
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unsigned int idx = clkspec->args[1]; |
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if (type == CP110_CLK_TYPE_CORE) { |
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if (idx >= CP110_MAX_CORE_CLOCKS) |
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return ERR_PTR(-EINVAL); |
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return clk_data->hws[idx]; |
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} else if (type == CP110_CLK_TYPE_GATABLE) { |
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if (idx >= CP110_MAX_GATABLE_CLOCKS) |
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return ERR_PTR(-EINVAL); |
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return clk_data->hws[CP110_MAX_CORE_CLOCKS + idx]; |
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} |
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return ERR_PTR(-EINVAL); |
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} |
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static int cp110_syscon_common_probe(struct platform_device *pdev, |
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struct device_node *syscon_node) |
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{ |
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struct regmap *regmap; |
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struct device *dev = &pdev->dev; |
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struct device_node *np = dev->of_node; |
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const char *ppv2_name, *pll0_name, *core_name, *x2core_name, *nand_name, |
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*sdio_name; |
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struct clk_hw_onecell_data *cp110_clk_data; |
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struct clk_hw *hw, **cp110_clks; |
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u32 nand_clk_ctrl; |
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int i, ret; |
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char *gate_name[ARRAY_SIZE(gate_base_names)]; |
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regmap = syscon_node_to_regmap(syscon_node); |
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if (IS_ERR(regmap)) |
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return PTR_ERR(regmap); |
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ret = regmap_read(regmap, CP110_NAND_FLASH_CLK_CTRL_REG, |
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&nand_clk_ctrl); |
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if (ret) |
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return ret; |
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cp110_clk_data = devm_kzalloc(dev, struct_size(cp110_clk_data, hws, |
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CP110_CLK_NUM), |
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GFP_KERNEL); |
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if (!cp110_clk_data) |
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return -ENOMEM; |
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cp110_clks = cp110_clk_data->hws; |
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cp110_clk_data->num = CP110_CLK_NUM; |
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/* Register the PLL0 which is the root of the hw tree */ |
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pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0"); |
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hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0, |
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1000 * 1000 * 1000); |
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if (IS_ERR(hw)) { |
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ret = PTR_ERR(hw); |
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goto fail_pll0; |
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} |
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cp110_clks[CP110_CORE_PLL0] = hw; |
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/* PPv2 is PLL0/3 */ |
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ppv2_name = ap_cp_unique_name(dev, syscon_node, "ppv2-core"); |
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hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3); |
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if (IS_ERR(hw)) { |
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ret = PTR_ERR(hw); |
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goto fail_ppv2; |
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} |
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cp110_clks[CP110_CORE_PPV2] = hw; |
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/* X2CORE clock is PLL0/2 */ |
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x2core_name = ap_cp_unique_name(dev, syscon_node, "x2core"); |
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hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name, |
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0, 1, 2); |
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if (IS_ERR(hw)) { |
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ret = PTR_ERR(hw); |
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goto fail_eip; |
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} |
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cp110_clks[CP110_CORE_X2CORE] = hw; |
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/* Core clock is X2CORE/2 */ |
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core_name = ap_cp_unique_name(dev, syscon_node, "core"); |
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hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name, |
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0, 1, 2); |
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if (IS_ERR(hw)) { |
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ret = PTR_ERR(hw); |
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goto fail_core; |
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} |
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cp110_clks[CP110_CORE_CORE] = hw; |
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/* NAND can be either PLL0/2.5 or core clock */ |
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nand_name = ap_cp_unique_name(dev, syscon_node, "nand-core"); |
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if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK) |
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hw = clk_hw_register_fixed_factor(NULL, nand_name, |
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pll0_name, 0, 2, 5); |
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else |
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hw = clk_hw_register_fixed_factor(NULL, nand_name, |
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core_name, 0, 1, 1); |
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if (IS_ERR(hw)) { |
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ret = PTR_ERR(hw); |
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goto fail_nand; |
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} |
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cp110_clks[CP110_CORE_NAND] = hw; |
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/* SDIO clock is PLL0/2.5 */ |
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sdio_name = ap_cp_unique_name(dev, syscon_node, "sdio-core"); |
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hw = clk_hw_register_fixed_factor(NULL, sdio_name, |
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pll0_name, 0, 2, 5); |
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if (IS_ERR(hw)) { |
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ret = PTR_ERR(hw); |
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goto fail_sdio; |
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} |
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cp110_clks[CP110_CORE_SDIO] = hw; |
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/* create the unique name for all the gate clocks */ |
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for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) |
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gate_name[i] = ap_cp_unique_name(dev, syscon_node, |
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gate_base_names[i]); |
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for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) { |
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const char *parent; |
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if (gate_name[i] == NULL) |
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continue; |
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switch (i) { |
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case CP110_GATE_NAND: |
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parent = nand_name; |
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break; |
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case CP110_GATE_MG: |
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case CP110_GATE_GOP_DP: |
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case CP110_GATE_PPV2: |
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parent = ppv2_name; |
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break; |
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case CP110_GATE_SDIO: |
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parent = sdio_name; |
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break; |
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case CP110_GATE_MAIN: |
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case CP110_GATE_PCIE_XOR: |
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case CP110_GATE_PCIE_X4: |
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case CP110_GATE_EIP150: |
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case CP110_GATE_EIP197: |
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parent = x2core_name; |
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break; |
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default: |
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parent = core_name; |
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break; |
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} |
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hw = cp110_register_gate(gate_name[i], parent, regmap, i); |
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if (IS_ERR(hw)) { |
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ret = PTR_ERR(hw); |
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goto fail_gate; |
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} |
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cp110_clks[CP110_MAX_CORE_CLOCKS + i] = hw; |
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} |
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ret = of_clk_add_hw_provider(np, cp110_of_clk_get, cp110_clk_data); |
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if (ret) |
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goto fail_clk_add; |
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platform_set_drvdata(pdev, cp110_clks); |
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return 0; |
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fail_clk_add: |
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fail_gate: |
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for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) { |
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hw = cp110_clks[CP110_MAX_CORE_CLOCKS + i]; |
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if (hw) |
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cp110_unregister_gate(hw); |
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} |
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_SDIO]); |
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fail_sdio: |
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]); |
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fail_nand: |
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]); |
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fail_core: |
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_X2CORE]); |
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fail_eip: |
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]); |
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fail_ppv2: |
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clk_hw_unregister_fixed_rate(cp110_clks[CP110_CORE_PLL0]); |
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fail_pll0: |
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return ret; |
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} |
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static int cp110_syscon_legacy_clk_probe(struct platform_device *pdev) |
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{ |
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dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n"); |
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dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n"); |
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dev_warn(&pdev->dev, FW_WARN |
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"This binding won't be supported in future kernels\n"); |
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return cp110_syscon_common_probe(pdev, pdev->dev.of_node); |
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} |
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static int cp110_clk_probe(struct platform_device *pdev) |
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{ |
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return cp110_syscon_common_probe(pdev, pdev->dev.of_node->parent); |
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} |
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static const struct of_device_id cp110_syscon_legacy_of_match[] = { |
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{ .compatible = "marvell,cp110-system-controller0", }, |
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{ } |
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}; |
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static struct platform_driver cp110_syscon_legacy_driver = { |
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.probe = cp110_syscon_legacy_clk_probe, |
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.driver = { |
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.name = "marvell-cp110-system-controller0", |
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.of_match_table = cp110_syscon_legacy_of_match, |
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.suppress_bind_attrs = true, |
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}, |
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}; |
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builtin_platform_driver(cp110_syscon_legacy_driver); |
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static const struct of_device_id cp110_clock_of_match[] = { |
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{ .compatible = "marvell,cp110-clock", }, |
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{ } |
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}; |
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static struct platform_driver cp110_clock_driver = { |
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.probe = cp110_clk_probe, |
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.driver = { |
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.name = "marvell-cp110-clock", |
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.of_match_table = cp110_clock_of_match, |
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.suppress_bind_attrs = true, |
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}, |
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}; |
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builtin_platform_driver(cp110_clock_driver);
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