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294 lines
6.8 KiB
294 lines
6.8 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Marvell EBU SoC common clock handling |
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* |
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* Copyright (C) 2012 Marvell |
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* |
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* Gregory CLEMENT <[email protected]> |
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* Sebastian Hesselbarth <[email protected]> |
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* Andrew Lunn <[email protected]> |
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* |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/slab.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/syscore_ops.h> |
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#include "common.h" |
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/* |
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* Core Clocks |
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*/ |
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#define SSCG_CONF_MODE(reg) (((reg) >> 16) & 0x3) |
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#define SSCG_SPREAD_DOWN 0x0 |
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#define SSCG_SPREAD_UP 0x1 |
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#define SSCG_SPREAD_CENTRAL 0x2 |
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#define SSCG_CONF_LOW(reg) (((reg) >> 8) & 0xFF) |
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#define SSCG_CONF_HIGH(reg) ((reg) & 0xFF) |
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static struct clk_onecell_data clk_data; |
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/* |
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* This function can be used by the Kirkwood, the Armada 370, the |
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* Armada XP and the Armada 375 SoC. The name of the function was |
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* chosen following the dt convention: using the first known SoC |
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* compatible with it. |
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*/ |
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u32 kirkwood_fix_sscg_deviation(u32 system_clk) |
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{ |
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struct device_node *sscg_np = NULL; |
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void __iomem *sscg_map; |
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u32 sscg_reg; |
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s32 low_bound, high_bound; |
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u64 freq_swing_half; |
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sscg_np = of_find_node_by_name(NULL, "sscg"); |
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if (sscg_np == NULL) { |
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pr_err("cannot get SSCG register node\n"); |
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return system_clk; |
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} |
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sscg_map = of_iomap(sscg_np, 0); |
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if (sscg_map == NULL) { |
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pr_err("cannot map SSCG register\n"); |
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goto out; |
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} |
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sscg_reg = readl(sscg_map); |
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high_bound = SSCG_CONF_HIGH(sscg_reg); |
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low_bound = SSCG_CONF_LOW(sscg_reg); |
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if ((high_bound - low_bound) <= 0) |
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goto out; |
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/* |
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* From Marvell engineer we got the following formula (when |
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* this code was written, the datasheet was erroneous) |
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* Spread percentage = 1/96 * (H - L) / H |
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* H = SSCG_High_Boundary |
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* L = SSCG_Low_Boundary |
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* |
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* As the deviation is half of spread then it lead to the |
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* following formula in the code. |
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* |
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* To avoid an overflow and not lose any significant digit in |
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* the same time we have to use a 64 bit integer. |
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*/ |
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freq_swing_half = (((u64)high_bound - (u64)low_bound) |
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* (u64)system_clk); |
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do_div(freq_swing_half, (2 * 96 * high_bound)); |
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switch (SSCG_CONF_MODE(sscg_reg)) { |
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case SSCG_SPREAD_DOWN: |
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system_clk -= freq_swing_half; |
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break; |
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case SSCG_SPREAD_UP: |
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system_clk += freq_swing_half; |
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break; |
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case SSCG_SPREAD_CENTRAL: |
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default: |
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break; |
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} |
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iounmap(sscg_map); |
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out: |
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of_node_put(sscg_np); |
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return system_clk; |
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} |
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void __init mvebu_coreclk_setup(struct device_node *np, |
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const struct coreclk_soc_desc *desc) |
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{ |
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const char *tclk_name = "tclk"; |
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const char *cpuclk_name = "cpuclk"; |
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void __iomem *base; |
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unsigned long rate; |
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int n; |
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base = of_iomap(np, 0); |
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if (WARN_ON(!base)) |
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return; |
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/* Allocate struct for TCLK, cpu clk, and core ratio clocks */ |
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clk_data.clk_num = 2 + desc->num_ratios; |
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/* One more clock for the optional refclk */ |
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if (desc->get_refclk_freq) |
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clk_data.clk_num += 1; |
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clk_data.clks = kcalloc(clk_data.clk_num, sizeof(*clk_data.clks), |
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GFP_KERNEL); |
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if (WARN_ON(!clk_data.clks)) { |
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iounmap(base); |
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return; |
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} |
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/* Register TCLK */ |
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of_property_read_string_index(np, "clock-output-names", 0, |
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&tclk_name); |
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rate = desc->get_tclk_freq(base); |
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clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, 0, |
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rate); |
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WARN_ON(IS_ERR(clk_data.clks[0])); |
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/* Register CPU clock */ |
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of_property_read_string_index(np, "clock-output-names", 1, |
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&cpuclk_name); |
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rate = desc->get_cpu_freq(base); |
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if (desc->is_sscg_enabled && desc->fix_sscg_deviation |
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&& desc->is_sscg_enabled(base)) |
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rate = desc->fix_sscg_deviation(rate); |
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clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, 0, |
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rate); |
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WARN_ON(IS_ERR(clk_data.clks[1])); |
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/* Register fixed-factor clocks derived from CPU clock */ |
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for (n = 0; n < desc->num_ratios; n++) { |
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const char *rclk_name = desc->ratios[n].name; |
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int mult, div; |
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of_property_read_string_index(np, "clock-output-names", |
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2+n, &rclk_name); |
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desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div); |
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clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name, |
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cpuclk_name, 0, mult, div); |
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WARN_ON(IS_ERR(clk_data.clks[2+n])); |
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} |
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/* Register optional refclk */ |
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if (desc->get_refclk_freq) { |
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const char *name = "refclk"; |
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of_property_read_string_index(np, "clock-output-names", |
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2 + desc->num_ratios, &name); |
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rate = desc->get_refclk_freq(base); |
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clk_data.clks[2 + desc->num_ratios] = |
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clk_register_fixed_rate(NULL, name, NULL, 0, rate); |
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WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios])); |
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} |
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/* SAR register isn't needed anymore */ |
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iounmap(base); |
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
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} |
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/* |
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* Clock Gating Control |
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*/ |
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DEFINE_SPINLOCK(ctrl_gating_lock); |
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struct clk_gating_ctrl { |
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spinlock_t *lock; |
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struct clk **gates; |
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int num_gates; |
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void __iomem *base; |
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u32 saved_reg; |
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}; |
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static struct clk_gating_ctrl *ctrl; |
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static struct clk *clk_gating_get_src( |
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struct of_phandle_args *clkspec, void *data) |
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{ |
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int n; |
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if (clkspec->args_count < 1) |
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return ERR_PTR(-EINVAL); |
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for (n = 0; n < ctrl->num_gates; n++) { |
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struct clk_gate *gate = |
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to_clk_gate(__clk_get_hw(ctrl->gates[n])); |
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if (clkspec->args[0] == gate->bit_idx) |
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return ctrl->gates[n]; |
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} |
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return ERR_PTR(-ENODEV); |
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} |
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static int mvebu_clk_gating_suspend(void) |
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{ |
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ctrl->saved_reg = readl(ctrl->base); |
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return 0; |
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} |
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static void mvebu_clk_gating_resume(void) |
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{ |
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writel(ctrl->saved_reg, ctrl->base); |
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} |
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static struct syscore_ops clk_gate_syscore_ops = { |
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.suspend = mvebu_clk_gating_suspend, |
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.resume = mvebu_clk_gating_resume, |
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}; |
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void __init mvebu_clk_gating_setup(struct device_node *np, |
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const struct clk_gating_soc_desc *desc) |
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{ |
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struct clk *clk; |
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void __iomem *base; |
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const char *default_parent = NULL; |
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int n; |
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if (ctrl) { |
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pr_err("mvebu-clk-gating: cannot instantiate more than one gateable clock device\n"); |
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return; |
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} |
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base = of_iomap(np, 0); |
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if (WARN_ON(!base)) |
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return; |
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clk = of_clk_get(np, 0); |
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if (!IS_ERR(clk)) { |
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default_parent = __clk_get_name(clk); |
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clk_put(clk); |
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} |
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ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); |
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if (WARN_ON(!ctrl)) |
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goto ctrl_out; |
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/* lock must already be initialized */ |
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ctrl->lock = &ctrl_gating_lock; |
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ctrl->base = base; |
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/* Count, allocate, and register clock gates */ |
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for (n = 0; desc[n].name;) |
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n++; |
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ctrl->num_gates = n; |
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ctrl->gates = kcalloc(ctrl->num_gates, sizeof(*ctrl->gates), |
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GFP_KERNEL); |
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if (WARN_ON(!ctrl->gates)) |
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goto gates_out; |
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for (n = 0; n < ctrl->num_gates; n++) { |
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const char *parent = |
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(desc[n].parent) ? desc[n].parent : default_parent; |
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ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent, |
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desc[n].flags, base, desc[n].bit_idx, |
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0, ctrl->lock); |
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WARN_ON(IS_ERR(ctrl->gates[n])); |
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} |
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of_clk_add_provider(np, clk_gating_get_src, ctrl); |
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register_syscore_ops(&clk_gate_syscore_ops); |
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return; |
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gates_out: |
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kfree(ctrl); |
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ctrl_out: |
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iounmap(base); |
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}
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