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253 lines
6.5 KiB
253 lines
6.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Marvell MVEBU CPU clock handling. |
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* |
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* Copyright (C) 2012 Marvell |
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* |
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* Gregory CLEMENT <[email protected]> |
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* |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/slab.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/of_address.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/delay.h> |
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#include <linux/mvebu-pmsu.h> |
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#include <asm/smp_plat.h> |
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#define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET 0x0 |
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#define SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL 0xff |
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#define SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT 8 |
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#define SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET 0x8 |
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#define SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT 16 |
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#define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET 0xC |
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#define SYS_CTRL_CLK_DIVIDER_MASK 0x3F |
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#define PMU_DFS_RATIO_SHIFT 16 |
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#define PMU_DFS_RATIO_MASK 0x3F |
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#define MAX_CPU 4 |
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struct cpu_clk { |
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struct clk_hw hw; |
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int cpu; |
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const char *clk_name; |
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const char *parent_name; |
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void __iomem *reg_base; |
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void __iomem *pmu_dfs; |
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}; |
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static struct clk **clks; |
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static struct clk_onecell_data clk_data; |
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#define to_cpu_clk(p) container_of(p, struct cpu_clk, hw) |
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static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk, |
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unsigned long parent_rate) |
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{ |
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struct cpu_clk *cpuclk = to_cpu_clk(hwclk); |
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u32 reg, div; |
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reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); |
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div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; |
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return parent_rate / div; |
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} |
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static long clk_cpu_round_rate(struct clk_hw *hwclk, unsigned long rate, |
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unsigned long *parent_rate) |
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{ |
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/* Valid ratio are 1:1, 1:2 and 1:3 */ |
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u32 div; |
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div = *parent_rate / rate; |
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if (div == 0) |
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div = 1; |
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else if (div > 3) |
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div = 3; |
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return *parent_rate / div; |
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} |
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static int clk_cpu_off_set_rate(struct clk_hw *hwclk, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct cpu_clk *cpuclk = to_cpu_clk(hwclk); |
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u32 reg, div; |
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u32 reload_mask; |
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div = parent_rate / rate; |
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reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) |
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& (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8)))) |
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| (div << (cpuclk->cpu * 8)); |
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writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); |
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/* Set clock divider reload smooth bit mask */ |
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reload_mask = 1 << (20 + cpuclk->cpu); |
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reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) |
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| reload_mask; |
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writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); |
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/* Now trigger the clock update */ |
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reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) |
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| 1 << 24; |
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writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); |
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/* Wait for clocks to settle down then clear reload request */ |
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udelay(1000); |
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reg &= ~(reload_mask | 1 << 24); |
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writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); |
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udelay(1000); |
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return 0; |
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} |
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static int clk_cpu_on_set_rate(struct clk_hw *hwclk, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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u32 reg; |
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unsigned long fabric_div, target_div, cur_rate; |
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struct cpu_clk *cpuclk = to_cpu_clk(hwclk); |
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/* |
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* PMU DFS registers are not mapped, Device Tree does not |
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* describes them. We cannot change the frequency dynamically. |
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*/ |
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if (!cpuclk->pmu_dfs) |
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return -ENODEV; |
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cur_rate = clk_hw_get_rate(hwclk); |
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reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET); |
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fabric_div = (reg >> SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT) & |
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SYS_CTRL_CLK_DIVIDER_MASK; |
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/* Frequency is going up */ |
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if (rate == 2 * cur_rate) |
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target_div = fabric_div / 2; |
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/* Frequency is going down */ |
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else |
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target_div = fabric_div; |
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if (target_div == 0) |
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target_div = 1; |
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reg = readl(cpuclk->pmu_dfs); |
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reg &= ~(PMU_DFS_RATIO_MASK << PMU_DFS_RATIO_SHIFT); |
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reg |= (target_div << PMU_DFS_RATIO_SHIFT); |
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writel(reg, cpuclk->pmu_dfs); |
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reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); |
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reg |= (SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL << |
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SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT); |
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writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); |
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return mvebu_pmsu_dfs_request(cpuclk->cpu); |
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} |
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static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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if (__clk_is_enabled(hwclk->clk)) |
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return clk_cpu_on_set_rate(hwclk, rate, parent_rate); |
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else |
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return clk_cpu_off_set_rate(hwclk, rate, parent_rate); |
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} |
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static const struct clk_ops cpu_ops = { |
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.recalc_rate = clk_cpu_recalc_rate, |
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.round_rate = clk_cpu_round_rate, |
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.set_rate = clk_cpu_set_rate, |
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}; |
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static void __init of_cpu_clk_setup(struct device_node *node) |
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{ |
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struct cpu_clk *cpuclk; |
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void __iomem *clock_complex_base = of_iomap(node, 0); |
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void __iomem *pmu_dfs_base = of_iomap(node, 1); |
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int ncpus = 0; |
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struct device_node *dn; |
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if (clock_complex_base == NULL) { |
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pr_err("%s: clock-complex base register not set\n", |
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__func__); |
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return; |
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} |
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if (pmu_dfs_base == NULL) |
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pr_warn("%s: pmu-dfs base register not set, dynamic frequency scaling not available\n", |
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__func__); |
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for_each_of_cpu_node(dn) |
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ncpus++; |
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cpuclk = kcalloc(ncpus, sizeof(*cpuclk), GFP_KERNEL); |
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if (WARN_ON(!cpuclk)) |
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goto cpuclk_out; |
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clks = kcalloc(ncpus, sizeof(*clks), GFP_KERNEL); |
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if (WARN_ON(!clks)) |
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goto clks_out; |
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for_each_of_cpu_node(dn) { |
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struct clk_init_data init; |
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struct clk *clk; |
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char *clk_name = kzalloc(5, GFP_KERNEL); |
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int cpu, err; |
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if (WARN_ON(!clk_name)) |
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goto bail_out; |
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err = of_property_read_u32(dn, "reg", &cpu); |
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if (WARN_ON(err)) |
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goto bail_out; |
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sprintf(clk_name, "cpu%d", cpu); |
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cpuclk[cpu].parent_name = of_clk_get_parent_name(node, 0); |
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cpuclk[cpu].clk_name = clk_name; |
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cpuclk[cpu].cpu = cpu; |
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cpuclk[cpu].reg_base = clock_complex_base; |
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if (pmu_dfs_base) |
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cpuclk[cpu].pmu_dfs = pmu_dfs_base + 4 * cpu; |
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cpuclk[cpu].hw.init = &init; |
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init.name = cpuclk[cpu].clk_name; |
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init.ops = &cpu_ops; |
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init.flags = 0; |
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init.parent_names = &cpuclk[cpu].parent_name; |
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init.num_parents = 1; |
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clk = clk_register(NULL, &cpuclk[cpu].hw); |
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if (WARN_ON(IS_ERR(clk))) |
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goto bail_out; |
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clks[cpu] = clk; |
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} |
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clk_data.clk_num = MAX_CPU; |
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clk_data.clks = clks; |
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of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data); |
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return; |
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bail_out: |
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kfree(clks); |
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while(ncpus--) |
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kfree(cpuclk[ncpus].clk_name); |
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clks_out: |
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kfree(cpuclk); |
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cpuclk_out: |
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iounmap(clock_complex_base); |
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} |
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CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock", |
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of_cpu_clk_setup); |
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static void __init of_mv98dx3236_cpu_clk_setup(struct device_node *node) |
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{ |
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of_clk_add_provider(node, of_clk_src_simple_get, NULL); |
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} |
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CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock", |
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of_mv98dx3236_cpu_clk_setup);
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