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184 lines
4.6 KiB
184 lines
4.6 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Marvell Armada 370 SoC clocks |
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* |
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* Copyright (C) 2012 Marvell |
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* |
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* Gregory CLEMENT <[email protected]> |
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* Sebastian Hesselbarth <[email protected]> |
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* Andrew Lunn <[email protected]> |
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* |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include "common.h" |
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/* |
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* Core Clocks |
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*/ |
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#define SARL 0 /* Low part [0:31] */ |
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#define SARL_A370_SSCG_ENABLE BIT(10) |
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#define SARL_A370_PCLK_FREQ_OPT 11 |
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#define SARL_A370_PCLK_FREQ_OPT_MASK 0xF |
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#define SARL_A370_FAB_FREQ_OPT 15 |
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#define SARL_A370_FAB_FREQ_OPT_MASK 0x1F |
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#define SARL_A370_TCLK_FREQ_OPT 20 |
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#define SARL_A370_TCLK_FREQ_OPT_MASK 0x1 |
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enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK }; |
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static const struct coreclk_ratio a370_coreclk_ratios[] __initconst = { |
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{ .id = A370_CPU_TO_NBCLK, .name = "nbclk" }, |
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{ .id = A370_CPU_TO_HCLK, .name = "hclk" }, |
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{ .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" }, |
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}; |
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static const u32 a370_tclk_freqs[] __initconst = { |
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166000000, |
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200000000, |
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}; |
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static u32 __init a370_get_tclk_freq(void __iomem *sar) |
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{ |
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u8 tclk_freq_select = 0; |
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tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) & |
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SARL_A370_TCLK_FREQ_OPT_MASK); |
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return a370_tclk_freqs[tclk_freq_select]; |
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} |
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static const u32 a370_cpu_freqs[] __initconst = { |
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400000000, |
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533000000, |
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667000000, |
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800000000, |
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1000000000, |
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1067000000, |
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1200000000, |
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}; |
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static u32 __init a370_get_cpu_freq(void __iomem *sar) |
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{ |
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u32 cpu_freq; |
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u8 cpu_freq_select = 0; |
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cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) & |
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SARL_A370_PCLK_FREQ_OPT_MASK); |
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if (cpu_freq_select >= ARRAY_SIZE(a370_cpu_freqs)) { |
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pr_err("CPU freq select unsupported %d\n", cpu_freq_select); |
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cpu_freq = 0; |
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} else |
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cpu_freq = a370_cpu_freqs[cpu_freq_select]; |
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return cpu_freq; |
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} |
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static const int a370_nbclk_ratios[32][2] __initconst = { |
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{0, 1}, {1, 2}, {2, 2}, {2, 2}, |
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{1, 2}, {1, 2}, {1, 1}, {2, 3}, |
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{0, 1}, {1, 2}, {2, 4}, {0, 1}, |
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{1, 2}, {0, 1}, {0, 1}, {2, 2}, |
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{0, 1}, {0, 1}, {0, 1}, {1, 1}, |
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{2, 3}, {0, 1}, {0, 1}, {0, 1}, |
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{0, 1}, {0, 1}, {0, 1}, {1, 1}, |
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{0, 1}, {0, 1}, {0, 1}, {0, 1}, |
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}; |
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static const int a370_hclk_ratios[32][2] __initconst = { |
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{0, 1}, {1, 2}, {2, 6}, {2, 3}, |
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{1, 3}, {1, 4}, {1, 2}, {2, 6}, |
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{0, 1}, {1, 6}, {2, 10}, {0, 1}, |
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{1, 4}, {0, 1}, {0, 1}, {2, 5}, |
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{0, 1}, {0, 1}, {0, 1}, {1, 2}, |
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{2, 6}, {0, 1}, {0, 1}, {0, 1}, |
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{0, 1}, {0, 1}, {0, 1}, {1, 1}, |
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{0, 1}, {0, 1}, {0, 1}, {0, 1}, |
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}; |
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static const int a370_dramclk_ratios[32][2] __initconst = { |
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{0, 1}, {1, 2}, {2, 3}, {2, 3}, |
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{1, 3}, {1, 2}, {1, 2}, {2, 6}, |
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{0, 1}, {1, 3}, {2, 5}, {0, 1}, |
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{1, 4}, {0, 1}, {0, 1}, {2, 5}, |
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{0, 1}, {0, 1}, {0, 1}, {1, 1}, |
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{2, 3}, {0, 1}, {0, 1}, {0, 1}, |
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{0, 1}, {0, 1}, {0, 1}, {1, 1}, |
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{0, 1}, {0, 1}, {0, 1}, {0, 1}, |
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}; |
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static void __init a370_get_clk_ratio( |
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void __iomem *sar, int id, int *mult, int *div) |
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{ |
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u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) & |
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SARL_A370_FAB_FREQ_OPT_MASK); |
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switch (id) { |
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case A370_CPU_TO_NBCLK: |
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*mult = a370_nbclk_ratios[opt][0]; |
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*div = a370_nbclk_ratios[opt][1]; |
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break; |
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case A370_CPU_TO_HCLK: |
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*mult = a370_hclk_ratios[opt][0]; |
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*div = a370_hclk_ratios[opt][1]; |
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break; |
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case A370_CPU_TO_DRAMCLK: |
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*mult = a370_dramclk_ratios[opt][0]; |
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*div = a370_dramclk_ratios[opt][1]; |
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break; |
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} |
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} |
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static bool a370_is_sscg_enabled(void __iomem *sar) |
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{ |
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return !(readl(sar) & SARL_A370_SSCG_ENABLE); |
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} |
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static const struct coreclk_soc_desc a370_coreclks = { |
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.get_tclk_freq = a370_get_tclk_freq, |
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.get_cpu_freq = a370_get_cpu_freq, |
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.get_clk_ratio = a370_get_clk_ratio, |
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.is_sscg_enabled = a370_is_sscg_enabled, |
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.fix_sscg_deviation = kirkwood_fix_sscg_deviation, |
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.ratios = a370_coreclk_ratios, |
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.num_ratios = ARRAY_SIZE(a370_coreclk_ratios), |
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}; |
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/* |
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* Clock Gating Control |
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*/ |
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static const struct clk_gating_soc_desc a370_gating_desc[] __initconst = { |
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{ "audio", NULL, 0, 0 }, |
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{ "pex0_en", NULL, 1, 0 }, |
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{ "pex1_en", NULL, 2, 0 }, |
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{ "ge1", NULL, 3, 0 }, |
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{ "ge0", NULL, 4, 0 }, |
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{ "pex0", "pex0_en", 5, 0 }, |
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{ "pex1", "pex1_en", 9, 0 }, |
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{ "sata0", NULL, 15, 0 }, |
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{ "sdio", NULL, 17, 0 }, |
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{ "crypto", NULL, 23, CLK_IGNORE_UNUSED }, |
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{ "tdm", NULL, 25, 0 }, |
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{ "ddr", NULL, 28, CLK_IGNORE_UNUSED }, |
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{ "sata1", NULL, 30, 0 }, |
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{ } |
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}; |
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static void __init a370_clk_init(struct device_node *np) |
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{ |
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struct device_node *cgnp = |
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of_find_compatible_node(NULL, NULL, "marvell,armada-370-gating-clock"); |
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mvebu_coreclk_setup(np, &a370_coreclks); |
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if (cgnp) { |
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mvebu_clk_gating_setup(cgnp, a370_gating_desc); |
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of_node_put(cgnp); |
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} |
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} |
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CLK_OF_DECLARE(a370_clk, "marvell,armada-370-core-clock", a370_clk_init); |
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