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137 lines
3.6 KiB
137 lines
3.6 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (c) 2018 BayLibre, SAS. |
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* Author: Jerome Brunet <[email protected]> |
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*/ |
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#ifndef __CLK_REGMAP_H |
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#define __CLK_REGMAP_H |
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#include <linux/clk-provider.h> |
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#include <linux/regmap.h> |
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/** |
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* struct clk_regmap - regmap backed clock |
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* |
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* @hw: handle between common and hardware-specific interfaces |
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* @map: pointer to the regmap structure controlling the clock |
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* @data: data specific to the clock type |
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* |
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* Clock which is controlled by regmap backed registers. The actual type of |
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* of the clock is controlled by the clock_ops and data. |
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*/ |
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struct clk_regmap { |
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struct clk_hw hw; |
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struct regmap *map; |
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void *data; |
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}; |
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static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw) |
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{ |
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return container_of(hw, struct clk_regmap, hw); |
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} |
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/** |
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* struct clk_regmap_gate_data - regmap backed gate specific data |
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* |
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* @offset: offset of the register controlling gate |
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* @bit_idx: single bit controlling gate |
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* @flags: hardware-specific flags |
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* |
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* Flags: |
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* Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored |
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*/ |
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struct clk_regmap_gate_data { |
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unsigned int offset; |
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u8 bit_idx; |
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u8 flags; |
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}; |
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static inline struct clk_regmap_gate_data * |
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clk_get_regmap_gate_data(struct clk_regmap *clk) |
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{ |
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return (struct clk_regmap_gate_data *)clk->data; |
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} |
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extern const struct clk_ops clk_regmap_gate_ops; |
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extern const struct clk_ops clk_regmap_gate_ro_ops; |
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/** |
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* struct clk_regmap_div_data - regmap backed adjustable divider specific data |
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* |
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* @offset: offset of the register controlling the divider |
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* @shift: shift to the divider bit field |
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* @width: width of the divider bit field |
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* @table: array of value/divider pairs, last entry should have div = 0 |
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* |
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* Flags: |
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* Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored |
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*/ |
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struct clk_regmap_div_data { |
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unsigned int offset; |
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u8 shift; |
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u8 width; |
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u8 flags; |
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const struct clk_div_table *table; |
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}; |
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static inline struct clk_regmap_div_data * |
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clk_get_regmap_div_data(struct clk_regmap *clk) |
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{ |
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return (struct clk_regmap_div_data *)clk->data; |
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} |
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extern const struct clk_ops clk_regmap_divider_ops; |
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extern const struct clk_ops clk_regmap_divider_ro_ops; |
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/** |
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* struct clk_regmap_mux_data - regmap backed multiplexer clock specific data |
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* |
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* @hw: handle between common and hardware-specific interfaces |
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* @offset: offset of theregister controlling multiplexer |
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* @table: array of parent indexed register values |
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* @shift: shift to multiplexer bit field |
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* @mask: mask of mutliplexer bit field |
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* @flags: hardware-specific flags |
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* |
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* Flags: |
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* Same as clk_divider except CLK_MUX_HIWORD_MASK which is ignored |
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*/ |
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struct clk_regmap_mux_data { |
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unsigned int offset; |
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u32 *table; |
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u32 mask; |
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u8 shift; |
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u8 flags; |
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}; |
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static inline struct clk_regmap_mux_data * |
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clk_get_regmap_mux_data(struct clk_regmap *clk) |
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{ |
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return (struct clk_regmap_mux_data *)clk->data; |
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} |
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extern const struct clk_ops clk_regmap_mux_ops; |
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extern const struct clk_ops clk_regmap_mux_ro_ops; |
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#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ |
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struct clk_regmap _name = { \ |
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.data = &(struct clk_regmap_gate_data){ \ |
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.offset = (_reg), \ |
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.bit_idx = (_bit), \ |
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}, \ |
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.hw.init = &(struct clk_init_data) { \ |
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.name = #_name, \ |
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.ops = _ops, \ |
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.parent_hws = (const struct clk_hw *[]) { _pname }, \ |
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.num_parents = 1, \ |
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.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ |
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}, \ |
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} |
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#define MESON_PCLK(_name, _reg, _bit, _pname) \ |
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__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) |
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#define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ |
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__MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) |
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#endif /* __CLK_REGMAP_H */
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