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341 lines
9.0 KiB
341 lines
9.0 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* PLL clock driver for Keystone devices |
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* |
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* Copyright (C) 2013 Texas Instruments Inc. |
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* Murali Karicheri <[email protected]> |
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* Santosh Shilimkar <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/of_address.h> |
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#include <linux/of.h> |
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#include <linux/module.h> |
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#define PLLM_LOW_MASK 0x3f |
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#define PLLM_HIGH_MASK 0x7ffc0 |
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#define MAIN_PLLM_HIGH_MASK 0x7f000 |
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#define PLLM_HIGH_SHIFT 6 |
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#define PLLD_MASK 0x3f |
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#define CLKOD_MASK 0x780000 |
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#define CLKOD_SHIFT 19 |
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/** |
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* struct clk_pll_data - pll data structure |
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* @has_pllctrl: If set to non zero, lower 6 bits of multiplier is in pllm |
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* register of pll controller, else it is in the pll_ctrl0((bit 11-6) |
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* @phy_pllm: Physical address of PLLM in pll controller. Used when |
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* has_pllctrl is non zero. |
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* @phy_pll_ctl0: Physical address of PLL ctrl0. This could be that of |
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* Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL |
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* or PA PLL available on keystone2. These PLLs are controlled by |
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* this register. Main PLL is controlled by a PLL controller. |
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* @pllm: PLL register map address for multiplier bits |
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* @pllod: PLL register map address for post divider bits |
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* @pll_ctl0: PLL controller map address |
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* @pllm_lower_mask: multiplier lower mask |
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* @pllm_upper_mask: multiplier upper mask |
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* @pllm_upper_shift: multiplier upper shift |
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* @plld_mask: divider mask |
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* @clkod_mask: output divider mask |
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* @clkod_shift: output divider shift |
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* @plld_mask: divider mask |
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* @postdiv: Fixed post divider |
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*/ |
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struct clk_pll_data { |
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bool has_pllctrl; |
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u32 phy_pllm; |
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u32 phy_pll_ctl0; |
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void __iomem *pllm; |
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void __iomem *pllod; |
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void __iomem *pll_ctl0; |
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u32 pllm_lower_mask; |
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u32 pllm_upper_mask; |
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u32 pllm_upper_shift; |
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u32 plld_mask; |
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u32 clkod_mask; |
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u32 clkod_shift; |
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u32 postdiv; |
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}; |
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/** |
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* struct clk_pll - Main pll clock |
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* @hw: clk_hw for the pll |
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* @pll_data: PLL driver specific data |
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*/ |
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struct clk_pll { |
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struct clk_hw hw; |
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struct clk_pll_data *pll_data; |
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}; |
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#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) |
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static unsigned long clk_pllclk_recalc(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_pll *pll = to_clk_pll(hw); |
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struct clk_pll_data *pll_data = pll->pll_data; |
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unsigned long rate = parent_rate; |
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u32 mult = 0, prediv, postdiv, val; |
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/* |
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* get bits 0-5 of multiplier from pllctrl PLLM register |
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* if has_pllctrl is non zero |
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*/ |
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if (pll_data->has_pllctrl) { |
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val = readl(pll_data->pllm); |
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mult = (val & pll_data->pllm_lower_mask); |
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} |
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/* bit6-12 of PLLM is in Main PLL control register */ |
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val = readl(pll_data->pll_ctl0); |
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mult |= ((val & pll_data->pllm_upper_mask) |
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>> pll_data->pllm_upper_shift); |
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prediv = (val & pll_data->plld_mask); |
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if (!pll_data->has_pllctrl) |
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/* read post divider from od bits*/ |
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postdiv = ((val & pll_data->clkod_mask) >> |
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pll_data->clkod_shift) + 1; |
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else if (pll_data->pllod) { |
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postdiv = readl(pll_data->pllod); |
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postdiv = ((postdiv & pll_data->clkod_mask) >> |
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pll_data->clkod_shift) + 1; |
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} else |
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postdiv = pll_data->postdiv; |
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rate /= (prediv + 1); |
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rate = (rate * (mult + 1)); |
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rate /= postdiv; |
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return rate; |
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} |
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static const struct clk_ops clk_pll_ops = { |
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.recalc_rate = clk_pllclk_recalc, |
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}; |
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static struct clk *clk_register_pll(struct device *dev, |
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const char *name, |
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const char *parent_name, |
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struct clk_pll_data *pll_data) |
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{ |
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struct clk_init_data init; |
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struct clk_pll *pll; |
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struct clk *clk; |
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pll = kzalloc(sizeof(*pll), GFP_KERNEL); |
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if (!pll) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &clk_pll_ops; |
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init.flags = 0; |
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init.parent_names = (parent_name ? &parent_name : NULL); |
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init.num_parents = (parent_name ? 1 : 0); |
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pll->pll_data = pll_data; |
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pll->hw.init = &init; |
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clk = clk_register(NULL, &pll->hw); |
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if (IS_ERR(clk)) |
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goto out; |
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return clk; |
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out: |
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kfree(pll); |
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return NULL; |
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} |
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/** |
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* _of_pll_clk_init - PLL initialisation via DT |
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* @node: device tree node for this clock |
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* @pllctrl: If true, lower 6 bits of multiplier is in pllm register of |
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* pll controller, else it is in the control register0(bit 11-6) |
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*/ |
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static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) |
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{ |
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struct clk_pll_data *pll_data; |
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const char *parent_name; |
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struct clk *clk; |
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int i; |
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pll_data = kzalloc(sizeof(*pll_data), GFP_KERNEL); |
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if (!pll_data) { |
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pr_err("%s: Out of memory\n", __func__); |
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return; |
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} |
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parent_name = of_clk_get_parent_name(node, 0); |
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if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) { |
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/* assume the PLL has output divider register bits */ |
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pll_data->clkod_mask = CLKOD_MASK; |
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pll_data->clkod_shift = CLKOD_SHIFT; |
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/* |
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* Check if there is an post-divider register. If not |
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* assume od bits are part of control register. |
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*/ |
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i = of_property_match_string(node, "reg-names", |
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"post-divider"); |
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pll_data->pllod = of_iomap(node, i); |
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} |
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i = of_property_match_string(node, "reg-names", "control"); |
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pll_data->pll_ctl0 = of_iomap(node, i); |
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if (!pll_data->pll_ctl0) { |
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pr_err("%s: ioremap failed\n", __func__); |
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iounmap(pll_data->pllod); |
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goto out; |
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} |
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pll_data->pllm_lower_mask = PLLM_LOW_MASK; |
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pll_data->pllm_upper_shift = PLLM_HIGH_SHIFT; |
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pll_data->plld_mask = PLLD_MASK; |
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pll_data->has_pllctrl = pllctrl; |
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if (!pll_data->has_pllctrl) { |
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pll_data->pllm_upper_mask = PLLM_HIGH_MASK; |
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} else { |
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pll_data->pllm_upper_mask = MAIN_PLLM_HIGH_MASK; |
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i = of_property_match_string(node, "reg-names", "multiplier"); |
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pll_data->pllm = of_iomap(node, i); |
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if (!pll_data->pllm) { |
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iounmap(pll_data->pll_ctl0); |
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iounmap(pll_data->pllod); |
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goto out; |
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} |
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} |
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clk = clk_register_pll(NULL, node->name, parent_name, pll_data); |
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if (clk) { |
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of_clk_add_provider(node, of_clk_src_simple_get, clk); |
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return; |
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} |
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out: |
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pr_err("%s: error initializing pll %pOFn\n", __func__, node); |
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kfree(pll_data); |
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} |
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/** |
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* of_keystone_pll_clk_init - PLL initialisation DT wrapper |
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* @node: device tree node for this clock |
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*/ |
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static void __init of_keystone_pll_clk_init(struct device_node *node) |
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{ |
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_of_pll_clk_init(node, false); |
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} |
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CLK_OF_DECLARE(keystone_pll_clock, "ti,keystone,pll-clock", |
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of_keystone_pll_clk_init); |
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/** |
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* of_keystone_main_pll_clk_init - Main PLL initialisation DT wrapper |
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* @node: device tree node for this clock |
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*/ |
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static void __init of_keystone_main_pll_clk_init(struct device_node *node) |
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{ |
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_of_pll_clk_init(node, true); |
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} |
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CLK_OF_DECLARE(keystone_main_pll_clock, "ti,keystone,main-pll-clock", |
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of_keystone_main_pll_clk_init); |
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/** |
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* of_pll_div_clk_init - PLL divider setup function |
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* @node: device tree node for this clock |
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*/ |
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static void __init of_pll_div_clk_init(struct device_node *node) |
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{ |
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const char *parent_name; |
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void __iomem *reg; |
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u32 shift, mask; |
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struct clk *clk; |
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const char *clk_name = node->name; |
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of_property_read_string(node, "clock-output-names", &clk_name); |
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reg = of_iomap(node, 0); |
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if (!reg) { |
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pr_err("%s: ioremap failed\n", __func__); |
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return; |
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} |
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parent_name = of_clk_get_parent_name(node, 0); |
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if (!parent_name) { |
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pr_err("%s: missing parent clock\n", __func__); |
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iounmap(reg); |
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return; |
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} |
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if (of_property_read_u32(node, "bit-shift", &shift)) { |
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pr_err("%s: missing 'shift' property\n", __func__); |
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iounmap(reg); |
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return; |
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} |
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if (of_property_read_u32(node, "bit-mask", &mask)) { |
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pr_err("%s: missing 'bit-mask' property\n", __func__); |
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iounmap(reg); |
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return; |
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} |
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clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift, |
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mask, 0, NULL); |
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if (clk) { |
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of_clk_add_provider(node, of_clk_src_simple_get, clk); |
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} else { |
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pr_err("%s: error registering divider %s\n", __func__, clk_name); |
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iounmap(reg); |
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} |
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} |
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CLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init); |
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/** |
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* of_pll_mux_clk_init - PLL mux setup function |
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* @node: device tree node for this clock |
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*/ |
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static void __init of_pll_mux_clk_init(struct device_node *node) |
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{ |
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void __iomem *reg; |
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u32 shift, mask; |
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struct clk *clk; |
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const char *parents[2]; |
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const char *clk_name = node->name; |
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of_property_read_string(node, "clock-output-names", &clk_name); |
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reg = of_iomap(node, 0); |
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if (!reg) { |
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pr_err("%s: ioremap failed\n", __func__); |
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return; |
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} |
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of_clk_parent_fill(node, parents, 2); |
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if (!parents[0] || !parents[1]) { |
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pr_err("%s: missing parent clocks\n", __func__); |
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return; |
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} |
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if (of_property_read_u32(node, "bit-shift", &shift)) { |
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pr_err("%s: missing 'shift' property\n", __func__); |
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return; |
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} |
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if (of_property_read_u32(node, "bit-mask", &mask)) { |
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pr_err("%s: missing 'bit-mask' property\n", __func__); |
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return; |
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} |
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clk = clk_register_mux(NULL, clk_name, (const char **)&parents, |
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ARRAY_SIZE(parents) , 0, reg, shift, mask, |
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0, NULL); |
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if (clk) |
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of_clk_add_provider(node, of_clk_src_simple_get, clk); |
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else |
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pr_err("%s: error registering mux %s\n", __func__, clk_name); |
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} |
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CLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init); |
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MODULE_LICENSE("GPL"); |
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MODULE_DESCRIPTION("PLL clock driver for Keystone devices"); |
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MODULE_AUTHOR("Murali Karicheri <[email protected]>"); |
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MODULE_AUTHOR("Santosh Shilimkar <[email protected]>");
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