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454 lines
12 KiB
454 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* JZ4770 SoC CGU driver |
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* Copyright 2018, Paul Cercueil <[email protected]> |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <dt-bindings/clock/jz4770-cgu.h> |
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#include "cgu.h" |
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#include "pm.h" |
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/* |
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* CPM registers offset address definition |
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*/ |
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#define CGU_REG_CPCCR 0x00 |
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#define CGU_REG_LCR 0x04 |
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#define CGU_REG_CPPCR0 0x10 |
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#define CGU_REG_CLKGR0 0x20 |
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#define CGU_REG_OPCR 0x24 |
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#define CGU_REG_CLKGR1 0x28 |
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#define CGU_REG_CPPCR1 0x30 |
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#define CGU_REG_USBPCR1 0x48 |
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#define CGU_REG_USBCDR 0x50 |
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#define CGU_REG_I2SCDR 0x60 |
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#define CGU_REG_LPCDR 0x64 |
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#define CGU_REG_MSC0CDR 0x68 |
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#define CGU_REG_UHCCDR 0x6c |
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#define CGU_REG_SSICDR 0x74 |
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#define CGU_REG_CIMCDR 0x7c |
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#define CGU_REG_GPSCDR 0x80 |
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#define CGU_REG_PCMCDR 0x84 |
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#define CGU_REG_GPUCDR 0x88 |
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#define CGU_REG_MSC1CDR 0xA4 |
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#define CGU_REG_MSC2CDR 0xA8 |
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#define CGU_REG_BCHCDR 0xAC |
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/* bits within the OPCR register */ |
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#define OPCR_SPENDH BIT(5) /* UHC PHY suspend */ |
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/* bits within the USBPCR1 register */ |
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#define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */ |
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static struct ingenic_cgu *cgu; |
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static int jz4770_uhc_phy_enable(struct clk_hw *hw) |
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{ |
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void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; |
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void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; |
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writel(readl(reg_opcr) & ~OPCR_SPENDH, reg_opcr); |
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writel(readl(reg_usbpcr1) | USBPCR1_UHC_POWER, reg_usbpcr1); |
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return 0; |
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} |
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static void jz4770_uhc_phy_disable(struct clk_hw *hw) |
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{ |
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void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; |
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void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; |
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writel(readl(reg_usbpcr1) & ~USBPCR1_UHC_POWER, reg_usbpcr1); |
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writel(readl(reg_opcr) | OPCR_SPENDH, reg_opcr); |
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} |
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static int jz4770_uhc_phy_is_enabled(struct clk_hw *hw) |
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{ |
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void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; |
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void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; |
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return !(readl(reg_opcr) & OPCR_SPENDH) && |
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(readl(reg_usbpcr1) & USBPCR1_UHC_POWER); |
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} |
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static const struct clk_ops jz4770_uhc_phy_ops = { |
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.enable = jz4770_uhc_phy_enable, |
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.disable = jz4770_uhc_phy_disable, |
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.is_enabled = jz4770_uhc_phy_is_enabled, |
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}; |
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static const s8 pll_od_encoding[8] = { |
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0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, |
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}; |
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static const u8 jz4770_cgu_cpccr_div_table[] = { |
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1, 2, 3, 4, 6, 8, 12, |
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}; |
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static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { |
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/* External clocks */ |
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[JZ4770_CLK_EXT] = { "ext", CGU_CLK_EXT }, |
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[JZ4770_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, |
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/* PLLs */ |
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[JZ4770_CLK_PLL0] = { |
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"pll0", CGU_CLK_PLL, |
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.parents = { JZ4770_CLK_EXT }, |
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.pll = { |
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.reg = CGU_REG_CPPCR0, |
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.rate_multiplier = 1, |
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.m_shift = 24, |
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.m_bits = 7, |
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.m_offset = 1, |
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.n_shift = 18, |
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.n_bits = 5, |
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.n_offset = 1, |
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.od_shift = 16, |
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.od_bits = 2, |
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.od_max = 8, |
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.od_encoding = pll_od_encoding, |
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.bypass_reg = CGU_REG_CPPCR0, |
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.bypass_bit = 9, |
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.enable_bit = 8, |
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.stable_bit = 10, |
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}, |
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}, |
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[JZ4770_CLK_PLL1] = { |
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/* TODO: PLL1 can depend on PLL0 */ |
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"pll1", CGU_CLK_PLL, |
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.parents = { JZ4770_CLK_EXT }, |
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.pll = { |
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.reg = CGU_REG_CPPCR1, |
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.rate_multiplier = 1, |
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.m_shift = 24, |
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.m_bits = 7, |
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.m_offset = 1, |
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.n_shift = 18, |
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.n_bits = 5, |
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.n_offset = 1, |
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.od_shift = 16, |
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.od_bits = 2, |
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.od_max = 8, |
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.od_encoding = pll_od_encoding, |
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.bypass_reg = CGU_REG_CPPCR1, |
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.no_bypass_bit = true, |
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.enable_bit = 7, |
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.stable_bit = 6, |
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}, |
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}, |
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/* Main clocks */ |
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[JZ4770_CLK_CCLK] = { |
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"cclk", CGU_CLK_DIV, |
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.parents = { JZ4770_CLK_PLL0, }, |
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.div = { |
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CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, |
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jz4770_cgu_cpccr_div_table, |
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}, |
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}, |
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[JZ4770_CLK_H0CLK] = { |
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"h0clk", CGU_CLK_DIV, |
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.parents = { JZ4770_CLK_PLL0, }, |
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.div = { |
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CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, |
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jz4770_cgu_cpccr_div_table, |
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}, |
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}, |
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[JZ4770_CLK_H1CLK] = { |
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"h1clk", CGU_CLK_DIV | CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_PLL0, }, |
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.div = { |
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CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, |
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jz4770_cgu_cpccr_div_table, |
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}, |
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.gate = { CGU_REG_CLKGR1, 7 }, |
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}, |
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[JZ4770_CLK_H2CLK] = { |
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"h2clk", CGU_CLK_DIV, |
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.parents = { JZ4770_CLK_PLL0, }, |
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.div = { |
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CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, |
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jz4770_cgu_cpccr_div_table, |
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}, |
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}, |
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[JZ4770_CLK_C1CLK] = { |
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"c1clk", CGU_CLK_DIV | CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_PLL0, }, |
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.div = { |
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CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, |
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jz4770_cgu_cpccr_div_table, |
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}, |
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.gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle |
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}, |
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[JZ4770_CLK_PCLK] = { |
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"pclk", CGU_CLK_DIV, |
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.parents = { JZ4770_CLK_PLL0, }, |
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.div = { |
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CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, |
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jz4770_cgu_cpccr_div_table, |
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}, |
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}, |
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/* Those divided clocks can connect to PLL0 or PLL1 */ |
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[JZ4770_CLK_MMC0_MUX] = { |
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"mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, |
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.mux = { CGU_REG_MSC0CDR, 30, 1 }, |
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.div = { CGU_REG_MSC0CDR, 0, 1, 7, -1, -1, 31 }, |
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.gate = { CGU_REG_MSC0CDR, 31 }, |
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}, |
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[JZ4770_CLK_MMC1_MUX] = { |
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"mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, |
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.mux = { CGU_REG_MSC1CDR, 30, 1 }, |
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.div = { CGU_REG_MSC1CDR, 0, 1, 7, -1, -1, 31 }, |
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.gate = { CGU_REG_MSC1CDR, 31 }, |
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}, |
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[JZ4770_CLK_MMC2_MUX] = { |
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"mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, |
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.mux = { CGU_REG_MSC2CDR, 30, 1 }, |
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.div = { CGU_REG_MSC2CDR, 0, 1, 7, -1, -1, 31 }, |
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.gate = { CGU_REG_MSC2CDR, 31 }, |
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}, |
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[JZ4770_CLK_CIM] = { |
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"cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, |
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.mux = { CGU_REG_CIMCDR, 31, 1 }, |
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.div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 26 }, |
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}, |
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[JZ4770_CLK_UHC] = { |
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"uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, |
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.mux = { CGU_REG_UHCCDR, 29, 1 }, |
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.div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 24 }, |
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}, |
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[JZ4770_CLK_GPU] = { |
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"gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, -1 }, |
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.mux = { CGU_REG_GPUCDR, 31, 1 }, |
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.div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR1, 9 }, |
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}, |
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[JZ4770_CLK_BCH] = { |
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"bch", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, |
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.mux = { CGU_REG_BCHCDR, 31, 1 }, |
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.div = { CGU_REG_BCHCDR, 0, 1, 3, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 1 }, |
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}, |
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[JZ4770_CLK_LPCLK_MUX] = { |
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"lpclk", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, |
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.mux = { CGU_REG_LPCDR, 29, 1 }, |
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.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 28 }, |
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}, |
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[JZ4770_CLK_GPS] = { |
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"gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_PLL0, JZ4770_CLK_PLL1, }, |
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.mux = { CGU_REG_GPSCDR, 31, 1 }, |
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.div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 22 }, |
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}, |
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/* Those divided clocks can connect to EXT, PLL0 or PLL1 */ |
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[JZ4770_CLK_SSI_MUX] = { |
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"ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_EXT, -1, |
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JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, |
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.mux = { CGU_REG_SSICDR, 30, 2 }, |
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.div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1 }, |
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}, |
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[JZ4770_CLK_PCM_MUX] = { |
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"pcm_mux", CGU_CLK_DIV | CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_EXT, -1, |
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JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, |
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.mux = { CGU_REG_PCMCDR, 30, 2 }, |
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.div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1 }, |
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}, |
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[JZ4770_CLK_I2S] = { |
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"i2s", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_EXT, -1, |
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JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, |
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.mux = { CGU_REG_I2SCDR, 30, 2 }, |
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.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR1, 13 }, |
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}, |
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[JZ4770_CLK_OTG] = { |
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"usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_EXT, -1, |
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JZ4770_CLK_PLL0, JZ4770_CLK_PLL1 }, |
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.mux = { CGU_REG_USBCDR, 30, 2 }, |
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.div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR0, 2 }, |
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}, |
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/* Gate-only clocks */ |
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[JZ4770_CLK_SSI0] = { |
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"ssi0", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_SSI_MUX, }, |
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.gate = { CGU_REG_CLKGR0, 4 }, |
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}, |
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[JZ4770_CLK_SSI1] = { |
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"ssi1", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_SSI_MUX, }, |
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.gate = { CGU_REG_CLKGR0, 19 }, |
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}, |
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[JZ4770_CLK_SSI2] = { |
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"ssi2", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_SSI_MUX, }, |
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.gate = { CGU_REG_CLKGR0, 20 }, |
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}, |
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[JZ4770_CLK_PCM0] = { |
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"pcm0", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_PCM_MUX, }, |
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.gate = { CGU_REG_CLKGR1, 8 }, |
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}, |
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[JZ4770_CLK_PCM1] = { |
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"pcm1", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_PCM_MUX, }, |
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.gate = { CGU_REG_CLKGR1, 10 }, |
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}, |
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[JZ4770_CLK_DMA] = { |
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"dma", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_H2CLK, }, |
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.gate = { CGU_REG_CLKGR0, 21 }, |
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}, |
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[JZ4770_CLK_I2C0] = { |
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"i2c0", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_EXT, }, |
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.gate = { CGU_REG_CLKGR0, 5 }, |
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}, |
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[JZ4770_CLK_I2C1] = { |
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"i2c1", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_EXT, }, |
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.gate = { CGU_REG_CLKGR0, 6 }, |
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}, |
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[JZ4770_CLK_I2C2] = { |
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"i2c2", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_EXT, }, |
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.gate = { CGU_REG_CLKGR1, 15 }, |
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}, |
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[JZ4770_CLK_UART0] = { |
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"uart0", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_EXT, }, |
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.gate = { CGU_REG_CLKGR0, 15 }, |
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}, |
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[JZ4770_CLK_UART1] = { |
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"uart1", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_EXT, }, |
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.gate = { CGU_REG_CLKGR0, 16 }, |
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}, |
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[JZ4770_CLK_UART2] = { |
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"uart2", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_EXT, }, |
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.gate = { CGU_REG_CLKGR0, 17 }, |
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}, |
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[JZ4770_CLK_UART3] = { |
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"uart3", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_EXT, }, |
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.gate = { CGU_REG_CLKGR0, 18 }, |
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}, |
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[JZ4770_CLK_IPU] = { |
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"ipu", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_H0CLK, }, |
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.gate = { CGU_REG_CLKGR0, 29 }, |
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}, |
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[JZ4770_CLK_ADC] = { |
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"adc", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_EXT, }, |
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.gate = { CGU_REG_CLKGR0, 14 }, |
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}, |
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[JZ4770_CLK_AIC] = { |
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"aic", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_EXT, }, |
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.gate = { CGU_REG_CLKGR0, 8 }, |
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}, |
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[JZ4770_CLK_AUX] = { |
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"aux", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_C1CLK, }, |
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.gate = { CGU_REG_CLKGR1, 14 }, |
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}, |
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[JZ4770_CLK_VPU] = { |
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"vpu", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_H1CLK, }, |
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.gate = { CGU_REG_LCR, 30, false, 150 }, |
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}, |
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[JZ4770_CLK_MMC0] = { |
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"mmc0", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_MMC0_MUX, }, |
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.gate = { CGU_REG_CLKGR0, 3 }, |
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}, |
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[JZ4770_CLK_MMC1] = { |
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"mmc1", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_MMC1_MUX, }, |
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.gate = { CGU_REG_CLKGR0, 11 }, |
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}, |
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[JZ4770_CLK_MMC2] = { |
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"mmc2", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_MMC2_MUX, }, |
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.gate = { CGU_REG_CLKGR0, 12 }, |
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}, |
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[JZ4770_CLK_OTG_PHY] = { |
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"usb_phy", CGU_CLK_GATE, |
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.parents = { JZ4770_CLK_OTG }, |
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.gate = { CGU_REG_OPCR, 7, true, 50 }, |
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}, |
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/* Custom clocks */ |
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[JZ4770_CLK_UHC_PHY] = { |
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"uhc_phy", CGU_CLK_CUSTOM, |
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.parents = { JZ4770_CLK_UHC, -1, -1, -1 }, |
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.custom = { &jz4770_uhc_phy_ops }, |
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}, |
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[JZ4770_CLK_EXT512] = { |
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"ext/512", CGU_CLK_FIXDIV, |
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.parents = { JZ4770_CLK_EXT }, |
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.fixdiv = { 512 }, |
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}, |
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[JZ4770_CLK_RTC] = { |
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"rtc", CGU_CLK_MUX, |
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.parents = { JZ4770_CLK_EXT512, JZ4770_CLK_OSC32K, }, |
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.mux = { CGU_REG_OPCR, 2, 1}, |
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}, |
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}; |
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static void __init jz4770_cgu_init(struct device_node *np) |
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{ |
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int retval; |
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cgu = ingenic_cgu_new(jz4770_cgu_clocks, |
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ARRAY_SIZE(jz4770_cgu_clocks), np); |
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if (!cgu) { |
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pr_err("%s: failed to initialise CGU\n", __func__); |
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return; |
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} |
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retval = ingenic_cgu_register_clocks(cgu); |
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if (retval) |
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pr_err("%s: failed to register CGU Clocks\n", __func__); |
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ingenic_cgu_register_syscore_ops(cgu); |
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} |
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/* We only probe via devicetree, no need for a platform driver */ |
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CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);
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