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264 lines
5.9 KiB
264 lines
5.9 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Ingenic JZ4725B SoC CGU driver |
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* |
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* Copyright (C) 2018 Paul Cercueil |
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* Author: Paul Cercueil <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/of.h> |
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#include <dt-bindings/clock/jz4725b-cgu.h> |
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#include "cgu.h" |
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#include "pm.h" |
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/* CGU register offsets */ |
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#define CGU_REG_CPCCR 0x00 |
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#define CGU_REG_LCR 0x04 |
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#define CGU_REG_CPPCR 0x10 |
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#define CGU_REG_CLKGR 0x20 |
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#define CGU_REG_OPCR 0x24 |
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#define CGU_REG_I2SCDR 0x60 |
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#define CGU_REG_LPCDR 0x64 |
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#define CGU_REG_MSCCDR 0x68 |
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#define CGU_REG_SSICDR 0x74 |
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#define CGU_REG_CIMCDR 0x78 |
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/* bits within the LCR register */ |
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#define LCR_SLEEP BIT(0) |
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static struct ingenic_cgu *cgu; |
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static const s8 pll_od_encoding[4] = { |
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0x0, 0x1, -1, 0x3, |
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}; |
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static const u8 jz4725b_cgu_cpccr_div_table[] = { |
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1, 2, 3, 4, 6, 8, |
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}; |
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static const u8 jz4725b_cgu_pll_half_div_table[] = { |
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2, 1, |
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}; |
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static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = { |
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/* External clocks */ |
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[JZ4725B_CLK_EXT] = { "ext", CGU_CLK_EXT }, |
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[JZ4725B_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, |
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[JZ4725B_CLK_PLL] = { |
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"pll", CGU_CLK_PLL, |
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.parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, |
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.pll = { |
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.reg = CGU_REG_CPPCR, |
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.rate_multiplier = 1, |
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.m_shift = 23, |
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.m_bits = 9, |
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.m_offset = 2, |
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.n_shift = 18, |
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.n_bits = 5, |
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.n_offset = 2, |
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.od_shift = 16, |
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.od_bits = 2, |
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.od_max = 4, |
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.od_encoding = pll_od_encoding, |
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.stable_bit = 10, |
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.bypass_reg = CGU_REG_CPPCR, |
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.bypass_bit = 9, |
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.enable_bit = 8, |
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}, |
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}, |
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/* Muxes & dividers */ |
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[JZ4725B_CLK_PLL_HALF] = { |
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"pll half", CGU_CLK_DIV, |
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.parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, |
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.div = { |
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CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, |
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jz4725b_cgu_pll_half_div_table, |
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}, |
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}, |
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[JZ4725B_CLK_CCLK] = { |
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"cclk", CGU_CLK_DIV, |
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.parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, |
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.div = { |
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CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, |
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jz4725b_cgu_cpccr_div_table, |
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}, |
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}, |
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[JZ4725B_CLK_HCLK] = { |
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"hclk", CGU_CLK_DIV, |
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.parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, |
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.div = { |
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CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, |
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jz4725b_cgu_cpccr_div_table, |
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}, |
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}, |
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[JZ4725B_CLK_PCLK] = { |
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"pclk", CGU_CLK_DIV, |
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.parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, |
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.div = { |
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CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, |
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jz4725b_cgu_cpccr_div_table, |
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}, |
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}, |
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[JZ4725B_CLK_MCLK] = { |
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"mclk", CGU_CLK_DIV, |
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.parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, |
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.div = { |
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CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, |
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jz4725b_cgu_cpccr_div_table, |
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}, |
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}, |
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[JZ4725B_CLK_IPU] = { |
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"ipu", CGU_CLK_DIV | CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_PLL, -1, -1, -1 }, |
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.div = { |
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CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, |
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jz4725b_cgu_cpccr_div_table, |
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}, |
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.gate = { CGU_REG_CLKGR, 13 }, |
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}, |
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[JZ4725B_CLK_LCD] = { |
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"lcd", CGU_CLK_DIV | CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 }, |
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.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR, 9 }, |
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}, |
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[JZ4725B_CLK_I2S] = { |
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"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 }, |
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.mux = { CGU_REG_CPCCR, 31, 1 }, |
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.div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR, 6 }, |
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}, |
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[JZ4725B_CLK_SPI] = { |
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"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 }, |
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.mux = { CGU_REG_SSICDR, 31, 1 }, |
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.div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR, 4 }, |
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}, |
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[JZ4725B_CLK_MMC_MUX] = { |
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"mmc_mux", CGU_CLK_DIV, |
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.parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 }, |
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.div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, |
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}, |
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[JZ4725B_CLK_UDC] = { |
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"udc", CGU_CLK_MUX | CGU_CLK_DIV, |
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.parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 }, |
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.mux = { CGU_REG_CPCCR, 29, 1 }, |
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.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, |
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}, |
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/* Gate-only clocks */ |
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[JZ4725B_CLK_UART] = { |
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"uart", CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR, 0 }, |
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}, |
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[JZ4725B_CLK_DMA] = { |
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"dma", CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_PCLK, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR, 12 }, |
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}, |
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[JZ4725B_CLK_ADC] = { |
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"adc", CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR, 7 }, |
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}, |
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[JZ4725B_CLK_I2C] = { |
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"i2c", CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR, 3 }, |
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}, |
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[JZ4725B_CLK_AIC] = { |
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"aic", CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR, 5 }, |
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}, |
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[JZ4725B_CLK_MMC0] = { |
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"mmc0", CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR, 6 }, |
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}, |
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[JZ4725B_CLK_MMC1] = { |
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"mmc1", CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR, 16 }, |
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}, |
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[JZ4725B_CLK_BCH] = { |
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"bch", CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR, 11 }, |
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}, |
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[JZ4725B_CLK_TCU] = { |
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"tcu", CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 }, |
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.gate = { CGU_REG_CLKGR, 1 }, |
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}, |
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[JZ4725B_CLK_EXT512] = { |
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"ext/512", CGU_CLK_FIXDIV, |
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.parents = { JZ4725B_CLK_EXT }, |
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/* Doc calls it EXT512, but it seems to be /256... */ |
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.fixdiv = { 256 }, |
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}, |
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[JZ4725B_CLK_RTC] = { |
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"rtc", CGU_CLK_MUX, |
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.parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 }, |
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.mux = { CGU_REG_OPCR, 2, 1}, |
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}, |
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[JZ4725B_CLK_UDC_PHY] = { |
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"udc_phy", CGU_CLK_GATE, |
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.parents = { JZ4725B_CLK_EXT, -1, -1, -1 }, |
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.gate = { CGU_REG_OPCR, 6, true }, |
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}, |
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}; |
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static void __init jz4725b_cgu_init(struct device_node *np) |
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{ |
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int retval; |
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cgu = ingenic_cgu_new(jz4725b_cgu_clocks, |
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ARRAY_SIZE(jz4725b_cgu_clocks), np); |
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if (!cgu) { |
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pr_err("%s: failed to initialise CGU\n", __func__); |
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return; |
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} |
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retval = ingenic_cgu_register_clocks(cgu); |
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if (retval) |
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pr_err("%s: failed to register CGU Clocks\n", __func__); |
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ingenic_cgu_register_syscore_ops(cgu); |
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} |
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CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);
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