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232 lines
7.4 KiB
232 lines
7.4 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Ingenic SoC CGU driver |
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* |
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* Copyright (c) 2013-2015 Imagination Technologies |
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* Author: Paul Burton <[email protected]> |
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*/ |
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#ifndef __DRIVERS_CLK_INGENIC_CGU_H__ |
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#define __DRIVERS_CLK_INGENIC_CGU_H__ |
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#include <linux/bitops.h> |
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#include <linux/clk-provider.h> |
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#include <linux/of.h> |
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#include <linux/spinlock.h> |
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/** |
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* struct ingenic_cgu_pll_info - information about a PLL |
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* @reg: the offset of the PLL's control register within the CGU |
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* @rate_multiplier: the multiplier needed by pll rate calculation |
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* @m_shift: the number of bits to shift the multiplier value by (ie. the |
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* index of the lowest bit of the multiplier value in the PLL's |
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* control register) |
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* @m_bits: the size of the multiplier field in bits |
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* @m_offset: the multiplier value which encodes to 0 in the PLL's control |
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* register |
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* @n_shift: the number of bits to shift the divider value by (ie. the |
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* index of the lowest bit of the divider value in the PLL's |
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* control register) |
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* @n_bits: the size of the divider field in bits |
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* @n_offset: the divider value which encodes to 0 in the PLL's control |
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* register |
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* @od_shift: the number of bits to shift the post-VCO divider value by (ie. |
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* the index of the lowest bit of the post-VCO divider value in |
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* the PLL's control register) |
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* @od_bits: the size of the post-VCO divider field in bits |
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* @od_max: the maximum post-VCO divider value |
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* @od_encoding: a pointer to an array mapping post-VCO divider values to |
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* their encoded values in the PLL control register, or -1 for |
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* unsupported values |
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* @bypass_reg: the offset of the bypass control register within the CGU |
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* @bypass_bit: the index of the bypass bit in the PLL control register |
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* @enable_bit: the index of the enable bit in the PLL control register |
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* @stable_bit: the index of the stable bit in the PLL control register |
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* @no_bypass_bit: if set, the PLL has no bypass functionality |
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*/ |
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struct ingenic_cgu_pll_info { |
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unsigned reg; |
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unsigned rate_multiplier; |
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const s8 *od_encoding; |
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u8 m_shift, m_bits, m_offset; |
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u8 n_shift, n_bits, n_offset; |
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u8 od_shift, od_bits, od_max; |
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unsigned bypass_reg; |
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u8 bypass_bit; |
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u8 enable_bit; |
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u8 stable_bit; |
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bool no_bypass_bit; |
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}; |
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/** |
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* struct ingenic_cgu_mux_info - information about a clock mux |
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* @reg: offset of the mux control register within the CGU |
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* @shift: number of bits to shift the mux value by (ie. the index of |
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* the lowest bit of the mux value within its control register) |
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* @bits: the size of the mux value in bits |
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*/ |
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struct ingenic_cgu_mux_info { |
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unsigned reg; |
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u8 shift; |
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u8 bits; |
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}; |
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/** |
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* struct ingenic_cgu_div_info - information about a divider |
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* @reg: offset of the divider control register within the CGU |
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* @shift: number of bits to left shift the divide value by (ie. the index of |
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* the lowest bit of the divide value within its control register) |
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* @div: number to divide the divider value by (i.e. if the |
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* effective divider value is the value written to the register |
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* multiplied by some constant) |
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* @bits: the size of the divide value in bits |
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* @ce_bit: the index of the change enable bit within reg, or -1 if there |
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* isn't one |
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* @busy_bit: the index of the busy bit within reg, or -1 if there isn't one |
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* @stop_bit: the index of the stop bit within reg, or -1 if there isn't one |
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* @div_table: optional table to map the value read from the register to the |
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* actual divider value |
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*/ |
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struct ingenic_cgu_div_info { |
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unsigned reg; |
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u8 shift; |
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u8 div; |
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u8 bits; |
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s8 ce_bit; |
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s8 busy_bit; |
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s8 stop_bit; |
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const u8 *div_table; |
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}; |
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/** |
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* struct ingenic_cgu_fixdiv_info - information about a fixed divider |
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* @div: the divider applied to the parent clock |
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*/ |
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struct ingenic_cgu_fixdiv_info { |
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unsigned div; |
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}; |
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/** |
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* struct ingenic_cgu_gate_info - information about a clock gate |
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* @reg: offset of the gate control register within the CGU |
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* @bit: offset of the bit in the register that controls the gate |
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* @clear_to_gate: if set, the clock is gated when the bit is cleared |
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* @delay_us: delay in microseconds after which the clock is considered stable |
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*/ |
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struct ingenic_cgu_gate_info { |
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unsigned reg; |
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u8 bit; |
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bool clear_to_gate; |
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u16 delay_us; |
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}; |
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/** |
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* struct ingenic_cgu_custom_info - information about a custom (SoC) clock |
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* @clk_ops: custom clock operation callbacks |
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*/ |
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struct ingenic_cgu_custom_info { |
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const struct clk_ops *clk_ops; |
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}; |
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/** |
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* struct ingenic_cgu_clk_info - information about a clock |
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* @name: name of the clock |
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* @type: a bitmask formed from CGU_CLK_* values |
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* @parents: an array of the indices of potential parents of this clock |
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* within the clock_info array of the CGU, or -1 in entries |
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* which correspond to no valid parent |
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* @pll: information valid if type includes CGU_CLK_PLL |
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* @gate: information valid if type includes CGU_CLK_GATE |
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* @mux: information valid if type includes CGU_CLK_MUX |
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* @div: information valid if type includes CGU_CLK_DIV |
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* @fixdiv: information valid if type includes CGU_CLK_FIXDIV |
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* @custom: information valid if type includes CGU_CLK_CUSTOM |
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*/ |
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struct ingenic_cgu_clk_info { |
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const char *name; |
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enum { |
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CGU_CLK_NONE = 0, |
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CGU_CLK_EXT = BIT(0), |
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CGU_CLK_PLL = BIT(1), |
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CGU_CLK_GATE = BIT(2), |
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CGU_CLK_MUX = BIT(3), |
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CGU_CLK_MUX_GLITCHFREE = BIT(4), |
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CGU_CLK_DIV = BIT(5), |
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CGU_CLK_FIXDIV = BIT(6), |
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CGU_CLK_CUSTOM = BIT(7), |
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} type; |
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int parents[4]; |
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union { |
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struct ingenic_cgu_pll_info pll; |
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struct { |
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struct ingenic_cgu_gate_info gate; |
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struct ingenic_cgu_mux_info mux; |
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struct ingenic_cgu_div_info div; |
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struct ingenic_cgu_fixdiv_info fixdiv; |
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}; |
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struct ingenic_cgu_custom_info custom; |
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}; |
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}; |
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/** |
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* struct ingenic_cgu - data about the CGU |
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* @np: the device tree node that caused the CGU to be probed |
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* @base: the ioremap'ed base address of the CGU registers |
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* @clock_info: an array containing information about implemented clocks |
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* @clocks: used to provide clocks to DT, allows lookup of struct clk* |
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* @lock: lock to be held whilst manipulating CGU registers |
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*/ |
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struct ingenic_cgu { |
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struct device_node *np; |
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void __iomem *base; |
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const struct ingenic_cgu_clk_info *clock_info; |
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struct clk_onecell_data clocks; |
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spinlock_t lock; |
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}; |
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/** |
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* struct ingenic_clk - private data for a clock |
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* @hw: see Documentation/driver-api/clk.rst |
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* @cgu: a pointer to the CGU data |
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* @idx: the index of this clock in cgu->clock_info |
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*/ |
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struct ingenic_clk { |
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struct clk_hw hw; |
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struct ingenic_cgu *cgu; |
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unsigned idx; |
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}; |
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#define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) |
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/** |
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* ingenic_cgu_new() - create a new CGU instance |
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* @clock_info: an array of clock information structures describing the clocks |
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* which are implemented by the CGU |
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* @num_clocks: the number of entries in clock_info |
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* @np: the device tree node which causes this CGU to be probed |
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* |
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* Return: a pointer to the CGU instance if initialisation is successful, |
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* otherwise NULL. |
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*/ |
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struct ingenic_cgu * |
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ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, |
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unsigned num_clocks, struct device_node *np); |
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/** |
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* ingenic_cgu_register_clocks() - Registers the clocks |
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* @cgu: pointer to cgu data |
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* |
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* Register the clocks described by the CGU with the common clock framework. |
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* |
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* Return: 0 on success or -errno if unsuccesful. |
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*/ |
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int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); |
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#endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */
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