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541 lines
13 KiB
541 lines
13 KiB
// SPDX-License-Identifier: (GPL-2.0 OR MIT) |
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/* |
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* Copyright 2018 NXP. |
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* |
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* This driver supports the SCCG plls found in the imx8m SOCs |
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* |
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* Documentation for this SCCG pll can be found at: |
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* https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834 |
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*/ |
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|
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#include <linux/clk-provider.h> |
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#include <linux/err.h> |
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#include <linux/export.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/slab.h> |
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#include <linux/bitfield.h> |
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#include "clk.h" |
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/* PLL CFGs */ |
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#define PLL_CFG0 0x0 |
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#define PLL_CFG1 0x4 |
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#define PLL_CFG2 0x8 |
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#define PLL_DIVF1_MASK GENMASK(18, 13) |
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#define PLL_DIVF2_MASK GENMASK(12, 7) |
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#define PLL_DIVR1_MASK GENMASK(27, 25) |
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#define PLL_DIVR2_MASK GENMASK(24, 19) |
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#define PLL_DIVQ_MASK GENMASK(6, 1) |
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#define PLL_REF_MASK GENMASK(2, 0) |
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#define PLL_LOCK_MASK BIT(31) |
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#define PLL_PD_MASK BIT(7) |
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/* These are the specification limits for the SSCG PLL */ |
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#define PLL_REF_MIN_FREQ 25000000UL |
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#define PLL_REF_MAX_FREQ 235000000UL |
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#define PLL_STAGE1_MIN_FREQ 1600000000UL |
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#define PLL_STAGE1_MAX_FREQ 2400000000UL |
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#define PLL_STAGE1_REF_MIN_FREQ 25000000UL |
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#define PLL_STAGE1_REF_MAX_FREQ 54000000UL |
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#define PLL_STAGE2_MIN_FREQ 1200000000UL |
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#define PLL_STAGE2_MAX_FREQ 2400000000UL |
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#define PLL_STAGE2_REF_MIN_FREQ 54000000UL |
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#define PLL_STAGE2_REF_MAX_FREQ 75000000UL |
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#define PLL_OUT_MIN_FREQ 20000000UL |
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#define PLL_OUT_MAX_FREQ 1200000000UL |
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#define PLL_DIVR1_MAX 7 |
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#define PLL_DIVR2_MAX 63 |
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#define PLL_DIVF1_MAX 63 |
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#define PLL_DIVF2_MAX 63 |
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#define PLL_DIVQ_MAX 63 |
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#define PLL_BYPASS_NONE 0x0 |
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#define PLL_BYPASS1 0x2 |
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#define PLL_BYPASS2 0x1 |
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#define SSCG_PLL_BYPASS1_MASK BIT(5) |
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#define SSCG_PLL_BYPASS2_MASK BIT(4) |
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#define SSCG_PLL_BYPASS_MASK GENMASK(5, 4) |
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#define PLL_SCCG_LOCK_TIMEOUT 70 |
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struct clk_sscg_pll_setup { |
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int divr1, divf1; |
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int divr2, divf2; |
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int divq; |
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int bypass; |
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uint64_t vco1; |
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uint64_t vco2; |
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uint64_t fout; |
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uint64_t ref; |
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uint64_t ref_div1; |
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uint64_t ref_div2; |
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uint64_t fout_request; |
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int fout_error; |
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}; |
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struct clk_sscg_pll { |
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struct clk_hw hw; |
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const struct clk_ops ops; |
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void __iomem *base; |
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struct clk_sscg_pll_setup setup; |
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u8 parent; |
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u8 bypass1; |
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u8 bypass2; |
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}; |
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#define to_clk_sscg_pll(_hw) container_of(_hw, struct clk_sscg_pll, hw) |
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static int clk_sscg_pll_wait_lock(struct clk_sscg_pll *pll) |
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{ |
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u32 val; |
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val = readl_relaxed(pll->base + PLL_CFG0); |
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/* don't wait for lock if all plls are bypassed */ |
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if (!(val & SSCG_PLL_BYPASS2_MASK)) |
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return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK, |
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0, PLL_SCCG_LOCK_TIMEOUT); |
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return 0; |
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} |
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static int clk_sscg_pll2_check_match(struct clk_sscg_pll_setup *setup, |
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struct clk_sscg_pll_setup *temp_setup) |
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{ |
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int new_diff = temp_setup->fout - temp_setup->fout_request; |
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int diff = temp_setup->fout_error; |
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if (abs(diff) > abs(new_diff)) { |
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temp_setup->fout_error = new_diff; |
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memcpy(setup, temp_setup, sizeof(struct clk_sscg_pll_setup)); |
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if (temp_setup->fout_request == temp_setup->fout) |
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return 0; |
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} |
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return -1; |
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} |
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static int clk_sscg_divq_lookup(struct clk_sscg_pll_setup *setup, |
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struct clk_sscg_pll_setup *temp_setup) |
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{ |
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int ret = -EINVAL; |
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for (temp_setup->divq = 0; temp_setup->divq <= PLL_DIVQ_MAX; |
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temp_setup->divq++) { |
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temp_setup->vco2 = temp_setup->vco1; |
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do_div(temp_setup->vco2, temp_setup->divr2 + 1); |
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temp_setup->vco2 *= 2; |
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temp_setup->vco2 *= temp_setup->divf2 + 1; |
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if (temp_setup->vco2 >= PLL_STAGE2_MIN_FREQ && |
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temp_setup->vco2 <= PLL_STAGE2_MAX_FREQ) { |
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temp_setup->fout = temp_setup->vco2; |
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do_div(temp_setup->fout, 2 * (temp_setup->divq + 1)); |
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ret = clk_sscg_pll2_check_match(setup, temp_setup); |
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if (!ret) { |
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temp_setup->bypass = PLL_BYPASS1; |
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return ret; |
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} |
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} |
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} |
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return ret; |
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} |
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static int clk_sscg_divf2_lookup(struct clk_sscg_pll_setup *setup, |
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struct clk_sscg_pll_setup *temp_setup) |
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{ |
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int ret = -EINVAL; |
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for (temp_setup->divf2 = 0; temp_setup->divf2 <= PLL_DIVF2_MAX; |
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temp_setup->divf2++) { |
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ret = clk_sscg_divq_lookup(setup, temp_setup); |
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if (!ret) |
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return ret; |
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} |
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return ret; |
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} |
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static int clk_sscg_divr2_lookup(struct clk_sscg_pll_setup *setup, |
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struct clk_sscg_pll_setup *temp_setup) |
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{ |
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int ret = -EINVAL; |
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for (temp_setup->divr2 = 0; temp_setup->divr2 <= PLL_DIVR2_MAX; |
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temp_setup->divr2++) { |
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temp_setup->ref_div2 = temp_setup->vco1; |
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do_div(temp_setup->ref_div2, temp_setup->divr2 + 1); |
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if (temp_setup->ref_div2 >= PLL_STAGE2_REF_MIN_FREQ && |
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temp_setup->ref_div2 <= PLL_STAGE2_REF_MAX_FREQ) { |
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ret = clk_sscg_divf2_lookup(setup, temp_setup); |
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if (!ret) |
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return ret; |
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} |
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} |
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return ret; |
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} |
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static int clk_sscg_pll2_find_setup(struct clk_sscg_pll_setup *setup, |
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struct clk_sscg_pll_setup *temp_setup, |
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uint64_t ref) |
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{ |
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int ret; |
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if (ref < PLL_STAGE1_MIN_FREQ || ref > PLL_STAGE1_MAX_FREQ) |
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return -EINVAL; |
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temp_setup->vco1 = ref; |
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ret = clk_sscg_divr2_lookup(setup, temp_setup); |
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return ret; |
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} |
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static int clk_sscg_divf1_lookup(struct clk_sscg_pll_setup *setup, |
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struct clk_sscg_pll_setup *temp_setup) |
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{ |
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int ret = -EINVAL; |
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for (temp_setup->divf1 = 0; temp_setup->divf1 <= PLL_DIVF1_MAX; |
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temp_setup->divf1++) { |
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uint64_t vco1 = temp_setup->ref; |
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do_div(vco1, temp_setup->divr1 + 1); |
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vco1 *= 2; |
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vco1 *= temp_setup->divf1 + 1; |
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ret = clk_sscg_pll2_find_setup(setup, temp_setup, vco1); |
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if (!ret) { |
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temp_setup->bypass = PLL_BYPASS_NONE; |
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return ret; |
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} |
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} |
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return ret; |
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} |
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static int clk_sscg_divr1_lookup(struct clk_sscg_pll_setup *setup, |
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struct clk_sscg_pll_setup *temp_setup) |
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{ |
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int ret = -EINVAL; |
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for (temp_setup->divr1 = 0; temp_setup->divr1 <= PLL_DIVR1_MAX; |
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temp_setup->divr1++) { |
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temp_setup->ref_div1 = temp_setup->ref; |
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do_div(temp_setup->ref_div1, temp_setup->divr1 + 1); |
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if (temp_setup->ref_div1 >= PLL_STAGE1_REF_MIN_FREQ && |
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temp_setup->ref_div1 <= PLL_STAGE1_REF_MAX_FREQ) { |
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ret = clk_sscg_divf1_lookup(setup, temp_setup); |
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if (!ret) |
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return ret; |
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} |
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} |
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return ret; |
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} |
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static int clk_sscg_pll1_find_setup(struct clk_sscg_pll_setup *setup, |
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struct clk_sscg_pll_setup *temp_setup, |
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uint64_t ref) |
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{ |
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int ret; |
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if (ref < PLL_REF_MIN_FREQ || ref > PLL_REF_MAX_FREQ) |
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return -EINVAL; |
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temp_setup->ref = ref; |
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ret = clk_sscg_divr1_lookup(setup, temp_setup); |
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return ret; |
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} |
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static int clk_sscg_pll_find_setup(struct clk_sscg_pll_setup *setup, |
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uint64_t prate, |
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uint64_t rate, int try_bypass) |
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{ |
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struct clk_sscg_pll_setup temp_setup; |
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int ret = -EINVAL; |
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memset(&temp_setup, 0, sizeof(struct clk_sscg_pll_setup)); |
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memset(setup, 0, sizeof(struct clk_sscg_pll_setup)); |
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temp_setup.fout_error = PLL_OUT_MAX_FREQ; |
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temp_setup.fout_request = rate; |
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switch (try_bypass) { |
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case PLL_BYPASS2: |
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if (prate == rate) { |
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setup->bypass = PLL_BYPASS2; |
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setup->fout = rate; |
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ret = 0; |
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} |
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break; |
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case PLL_BYPASS1: |
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ret = clk_sscg_pll2_find_setup(setup, &temp_setup, prate); |
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break; |
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case PLL_BYPASS_NONE: |
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ret = clk_sscg_pll1_find_setup(setup, &temp_setup, prate); |
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break; |
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} |
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return ret; |
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} |
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static int clk_sscg_pll_is_prepared(struct clk_hw *hw) |
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{ |
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struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); |
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u32 val = readl_relaxed(pll->base + PLL_CFG0); |
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return (val & PLL_PD_MASK) ? 0 : 1; |
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} |
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static int clk_sscg_pll_prepare(struct clk_hw *hw) |
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{ |
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struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); |
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u32 val; |
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val = readl_relaxed(pll->base + PLL_CFG0); |
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val &= ~PLL_PD_MASK; |
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writel_relaxed(val, pll->base + PLL_CFG0); |
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return clk_sscg_pll_wait_lock(pll); |
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} |
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static void clk_sscg_pll_unprepare(struct clk_hw *hw) |
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{ |
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struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); |
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u32 val; |
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val = readl_relaxed(pll->base + PLL_CFG0); |
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val |= PLL_PD_MASK; |
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writel_relaxed(val, pll->base + PLL_CFG0); |
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} |
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static unsigned long clk_sscg_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); |
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u32 val, divr1, divf1, divr2, divf2, divq; |
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u64 temp64; |
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val = readl_relaxed(pll->base + PLL_CFG2); |
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divr1 = FIELD_GET(PLL_DIVR1_MASK, val); |
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divr2 = FIELD_GET(PLL_DIVR2_MASK, val); |
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divf1 = FIELD_GET(PLL_DIVF1_MASK, val); |
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divf2 = FIELD_GET(PLL_DIVF2_MASK, val); |
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divq = FIELD_GET(PLL_DIVQ_MASK, val); |
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temp64 = parent_rate; |
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val = readl(pll->base + PLL_CFG0); |
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if (val & SSCG_PLL_BYPASS2_MASK) { |
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temp64 = parent_rate; |
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} else if (val & SSCG_PLL_BYPASS1_MASK) { |
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temp64 *= divf2; |
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do_div(temp64, (divr2 + 1) * (divq + 1)); |
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} else { |
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temp64 *= 2; |
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temp64 *= (divf1 + 1) * (divf2 + 1); |
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do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1)); |
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} |
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return temp64; |
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} |
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static int clk_sscg_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); |
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struct clk_sscg_pll_setup *setup = &pll->setup; |
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u32 val; |
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/* set bypass here too since the parent might be the same */ |
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val = readl(pll->base + PLL_CFG0); |
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val &= ~SSCG_PLL_BYPASS_MASK; |
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val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass); |
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writel(val, pll->base + PLL_CFG0); |
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val = readl_relaxed(pll->base + PLL_CFG2); |
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val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK); |
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val &= ~(PLL_DIVR1_MASK | PLL_DIVR2_MASK | PLL_DIVQ_MASK); |
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val |= FIELD_PREP(PLL_DIVF1_MASK, setup->divf1); |
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val |= FIELD_PREP(PLL_DIVF2_MASK, setup->divf2); |
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val |= FIELD_PREP(PLL_DIVR1_MASK, setup->divr1); |
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val |= FIELD_PREP(PLL_DIVR2_MASK, setup->divr2); |
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val |= FIELD_PREP(PLL_DIVQ_MASK, setup->divq); |
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writel_relaxed(val, pll->base + PLL_CFG2); |
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return clk_sscg_pll_wait_lock(pll); |
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} |
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static u8 clk_sscg_pll_get_parent(struct clk_hw *hw) |
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{ |
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struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); |
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u32 val; |
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u8 ret = pll->parent; |
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val = readl(pll->base + PLL_CFG0); |
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if (val & SSCG_PLL_BYPASS2_MASK) |
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ret = pll->bypass2; |
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else if (val & SSCG_PLL_BYPASS1_MASK) |
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ret = pll->bypass1; |
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return ret; |
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} |
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static int clk_sscg_pll_set_parent(struct clk_hw *hw, u8 index) |
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{ |
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struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); |
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u32 val; |
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val = readl(pll->base + PLL_CFG0); |
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val &= ~SSCG_PLL_BYPASS_MASK; |
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val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass); |
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writel(val, pll->base + PLL_CFG0); |
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return clk_sscg_pll_wait_lock(pll); |
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} |
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static int __clk_sscg_pll_determine_rate(struct clk_hw *hw, |
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struct clk_rate_request *req, |
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uint64_t min, |
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uint64_t max, |
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uint64_t rate, |
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int bypass) |
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{ |
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struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); |
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struct clk_sscg_pll_setup *setup = &pll->setup; |
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struct clk_hw *parent_hw = NULL; |
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int bypass_parent_index; |
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int ret; |
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req->max_rate = max; |
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req->min_rate = min; |
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switch (bypass) { |
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case PLL_BYPASS2: |
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bypass_parent_index = pll->bypass2; |
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break; |
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case PLL_BYPASS1: |
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bypass_parent_index = pll->bypass1; |
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break; |
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default: |
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bypass_parent_index = pll->parent; |
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break; |
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} |
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parent_hw = clk_hw_get_parent_by_index(hw, bypass_parent_index); |
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ret = __clk_determine_rate(parent_hw, req); |
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if (!ret) { |
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ret = clk_sscg_pll_find_setup(setup, req->rate, |
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rate, bypass); |
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} |
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req->best_parent_hw = parent_hw; |
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req->best_parent_rate = req->rate; |
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req->rate = setup->fout; |
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return ret; |
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} |
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static int clk_sscg_pll_determine_rate(struct clk_hw *hw, |
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struct clk_rate_request *req) |
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{ |
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struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); |
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struct clk_sscg_pll_setup *setup = &pll->setup; |
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uint64_t rate = req->rate; |
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uint64_t min = req->min_rate; |
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uint64_t max = req->max_rate; |
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int ret; |
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if (rate < PLL_OUT_MIN_FREQ || rate > PLL_OUT_MAX_FREQ) |
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return -EINVAL; |
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ret = __clk_sscg_pll_determine_rate(hw, req, req->rate, req->rate, |
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rate, PLL_BYPASS2); |
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if (!ret) |
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return ret; |
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ret = __clk_sscg_pll_determine_rate(hw, req, PLL_STAGE1_REF_MIN_FREQ, |
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PLL_STAGE1_REF_MAX_FREQ, rate, |
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PLL_BYPASS1); |
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if (!ret) |
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return ret; |
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|
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ret = __clk_sscg_pll_determine_rate(hw, req, PLL_REF_MIN_FREQ, |
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PLL_REF_MAX_FREQ, rate, |
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PLL_BYPASS_NONE); |
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if (!ret) |
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return ret; |
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|
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if (setup->fout >= min && setup->fout <= max) |
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ret = 0; |
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return ret; |
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} |
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|
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static const struct clk_ops clk_sscg_pll_ops = { |
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.prepare = clk_sscg_pll_prepare, |
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.unprepare = clk_sscg_pll_unprepare, |
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.is_prepared = clk_sscg_pll_is_prepared, |
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.recalc_rate = clk_sscg_pll_recalc_rate, |
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.set_rate = clk_sscg_pll_set_rate, |
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.set_parent = clk_sscg_pll_set_parent, |
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.get_parent = clk_sscg_pll_get_parent, |
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.determine_rate = clk_sscg_pll_determine_rate, |
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}; |
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struct clk_hw *imx_clk_hw_sscg_pll(const char *name, |
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const char * const *parent_names, |
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u8 num_parents, |
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u8 parent, u8 bypass1, u8 bypass2, |
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void __iomem *base, |
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unsigned long flags) |
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{ |
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struct clk_sscg_pll *pll; |
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struct clk_init_data init; |
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struct clk_hw *hw; |
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int ret; |
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|
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pll = kzalloc(sizeof(*pll), GFP_KERNEL); |
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if (!pll) |
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return ERR_PTR(-ENOMEM); |
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pll->parent = parent; |
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pll->bypass1 = bypass1; |
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pll->bypass2 = bypass2; |
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|
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pll->base = base; |
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init.name = name; |
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init.ops = &clk_sscg_pll_ops; |
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|
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init.flags = flags; |
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init.parent_names = parent_names; |
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init.num_parents = num_parents; |
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|
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pll->base = base; |
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pll->hw.init = &init; |
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|
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hw = &pll->hw; |
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|
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ret = clk_hw_register(NULL, hw); |
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if (ret) { |
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kfree(pll); |
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return ERR_PTR(ret); |
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} |
|
|
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return hw; |
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} |
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EXPORT_SYMBOL_GPL(imx_clk_hw_sscg_pll);
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