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606 lines
14 KiB
606 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2018 NXP |
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* Dong Aisheng <[email protected]> |
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*/ |
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|
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#include <dt-bindings/firmware/imx/rsrc.h> |
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#include <linux/arm-smccc.h> |
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#include <linux/clk-provider.h> |
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#include <linux/err.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_domain.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/slab.h> |
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#include "clk-scu.h" |
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#define IMX_SIP_CPUFREQ 0xC2000001 |
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#define IMX_SIP_SET_CPUFREQ 0x00 |
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static struct imx_sc_ipc *ccm_ipc_handle; |
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static struct device_node *pd_np; |
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static struct platform_driver imx_clk_scu_driver; |
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struct imx_scu_clk_node { |
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const char *name; |
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u32 rsrc; |
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u8 clk_type; |
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const char * const *parents; |
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int num_parents; |
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struct clk_hw *hw; |
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struct list_head node; |
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}; |
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struct list_head imx_scu_clks[IMX_SC_R_LAST]; |
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/* |
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* struct clk_scu - Description of one SCU clock |
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* @hw: the common clk_hw |
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* @rsrc_id: resource ID of this SCU clock |
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* @clk_type: type of this clock resource |
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*/ |
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struct clk_scu { |
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struct clk_hw hw; |
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u16 rsrc_id; |
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u8 clk_type; |
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/* for state save&restore */ |
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bool is_enabled; |
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u32 rate; |
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}; |
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/* |
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* struct imx_sc_msg_req_set_clock_rate - clock set rate protocol |
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* @hdr: SCU protocol header |
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* @rate: rate to set |
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* @resource: clock resource to set rate |
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* @clk: clk type of this resource |
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* |
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* This structure describes the SCU protocol of clock rate set |
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*/ |
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struct imx_sc_msg_req_set_clock_rate { |
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struct imx_sc_rpc_msg hdr; |
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__le32 rate; |
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__le16 resource; |
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u8 clk; |
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} __packed __aligned(4); |
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struct req_get_clock_rate { |
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__le16 resource; |
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u8 clk; |
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} __packed __aligned(4); |
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struct resp_get_clock_rate { |
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__le32 rate; |
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}; |
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/* |
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* struct imx_sc_msg_get_clock_rate - clock get rate protocol |
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* @hdr: SCU protocol header |
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* @req: get rate request protocol |
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* @resp: get rate response protocol |
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* |
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* This structure describes the SCU protocol of clock rate get |
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*/ |
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struct imx_sc_msg_get_clock_rate { |
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struct imx_sc_rpc_msg hdr; |
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union { |
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struct req_get_clock_rate req; |
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struct resp_get_clock_rate resp; |
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} data; |
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}; |
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/* |
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* struct imx_sc_msg_get_clock_parent - clock get parent protocol |
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* @hdr: SCU protocol header |
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* @req: get parent request protocol |
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* @resp: get parent response protocol |
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* |
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* This structure describes the SCU protocol of clock get parent |
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*/ |
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struct imx_sc_msg_get_clock_parent { |
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struct imx_sc_rpc_msg hdr; |
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union { |
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struct req_get_clock_parent { |
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__le16 resource; |
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u8 clk; |
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} __packed __aligned(4) req; |
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struct resp_get_clock_parent { |
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u8 parent; |
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} resp; |
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} data; |
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}; |
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/* |
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* struct imx_sc_msg_set_clock_parent - clock set parent protocol |
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* @hdr: SCU protocol header |
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* @req: set parent request protocol |
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* |
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* This structure describes the SCU protocol of clock set parent |
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*/ |
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struct imx_sc_msg_set_clock_parent { |
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struct imx_sc_rpc_msg hdr; |
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__le16 resource; |
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u8 clk; |
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u8 parent; |
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} __packed; |
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/* |
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* struct imx_sc_msg_req_clock_enable - clock gate protocol |
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* @hdr: SCU protocol header |
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* @resource: clock resource to gate |
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* @clk: clk type of this resource |
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* @enable: whether gate off the clock |
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* @autog: HW auto gate enable |
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* |
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* This structure describes the SCU protocol of clock gate |
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*/ |
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struct imx_sc_msg_req_clock_enable { |
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struct imx_sc_rpc_msg hdr; |
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__le16 resource; |
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u8 clk; |
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u8 enable; |
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u8 autog; |
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} __packed __aligned(4); |
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static inline struct clk_scu *to_clk_scu(struct clk_hw *hw) |
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{ |
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return container_of(hw, struct clk_scu, hw); |
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} |
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int imx_clk_scu_init(struct device_node *np) |
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{ |
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u32 clk_cells; |
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int ret, i; |
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ret = imx_scu_get_handle(&ccm_ipc_handle); |
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if (ret) |
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return ret; |
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of_property_read_u32(np, "#clock-cells", &clk_cells); |
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if (clk_cells == 2) { |
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for (i = 0; i < IMX_SC_R_LAST; i++) |
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INIT_LIST_HEAD(&imx_scu_clks[i]); |
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/* pd_np will be used to attach power domains later */ |
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pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd"); |
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if (!pd_np) |
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return -EINVAL; |
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} |
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return platform_driver_register(&imx_clk_scu_driver); |
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} |
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/* |
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* clk_scu_recalc_rate - Get clock rate for a SCU clock |
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* @hw: clock to get rate for |
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* @parent_rate: parent rate provided by common clock framework, not used |
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* |
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* Gets the current clock rate of a SCU clock. Returns the current |
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* clock rate, or zero in failure. |
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*/ |
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static unsigned long clk_scu_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_scu *clk = to_clk_scu(hw); |
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struct imx_sc_msg_get_clock_rate msg; |
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struct imx_sc_rpc_msg *hdr = &msg.hdr; |
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int ret; |
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hdr->ver = IMX_SC_RPC_VERSION; |
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hdr->svc = IMX_SC_RPC_SVC_PM; |
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hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_RATE; |
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hdr->size = 2; |
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msg.data.req.resource = cpu_to_le16(clk->rsrc_id); |
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msg.data.req.clk = clk->clk_type; |
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ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true); |
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if (ret) { |
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pr_err("%s: failed to get clock rate %d\n", |
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clk_hw_get_name(hw), ret); |
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return 0; |
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} |
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return le32_to_cpu(msg.data.resp.rate); |
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} |
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/* |
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* clk_scu_round_rate - Round clock rate for a SCU clock |
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* @hw: clock to round rate for |
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* @rate: rate to round |
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* @parent_rate: parent rate provided by common clock framework, not used |
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* |
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* Returns the current clock rate, or zero in failure. |
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*/ |
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static long clk_scu_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *parent_rate) |
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{ |
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/* |
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* Assume we support all the requested rate and let the SCU firmware |
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* to handle the left work |
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*/ |
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return rate; |
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} |
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static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct clk_scu *clk = to_clk_scu(hw); |
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struct arm_smccc_res res; |
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unsigned long cluster_id; |
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if (clk->rsrc_id == IMX_SC_R_A35) |
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cluster_id = 0; |
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else |
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return -EINVAL; |
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/* CPU frequency scaling can ONLY be done by ARM-Trusted-Firmware */ |
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arm_smccc_smc(IMX_SIP_CPUFREQ, IMX_SIP_SET_CPUFREQ, |
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cluster_id, rate, 0, 0, 0, 0, &res); |
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return 0; |
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} |
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/* |
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* clk_scu_set_rate - Set rate for a SCU clock |
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* @hw: clock to change rate for |
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* @rate: target rate for the clock |
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* @parent_rate: rate of the clock parent, not used for SCU clocks |
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* |
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* Sets a clock frequency for a SCU clock. Returns the SCU |
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* protocol status. |
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*/ |
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static int clk_scu_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct clk_scu *clk = to_clk_scu(hw); |
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struct imx_sc_msg_req_set_clock_rate msg; |
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struct imx_sc_rpc_msg *hdr = &msg.hdr; |
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hdr->ver = IMX_SC_RPC_VERSION; |
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hdr->svc = IMX_SC_RPC_SVC_PM; |
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hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_RATE; |
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hdr->size = 3; |
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msg.rate = cpu_to_le32(rate); |
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msg.resource = cpu_to_le16(clk->rsrc_id); |
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msg.clk = clk->clk_type; |
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return imx_scu_call_rpc(ccm_ipc_handle, &msg, true); |
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} |
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static u8 clk_scu_get_parent(struct clk_hw *hw) |
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{ |
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struct clk_scu *clk = to_clk_scu(hw); |
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struct imx_sc_msg_get_clock_parent msg; |
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struct imx_sc_rpc_msg *hdr = &msg.hdr; |
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int ret; |
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hdr->ver = IMX_SC_RPC_VERSION; |
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hdr->svc = IMX_SC_RPC_SVC_PM; |
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hdr->func = IMX_SC_PM_FUNC_GET_CLOCK_PARENT; |
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hdr->size = 2; |
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msg.data.req.resource = cpu_to_le16(clk->rsrc_id); |
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msg.data.req.clk = clk->clk_type; |
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ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true); |
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if (ret) { |
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pr_err("%s: failed to get clock parent %d\n", |
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clk_hw_get_name(hw), ret); |
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return 0; |
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} |
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return msg.data.resp.parent; |
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} |
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static int clk_scu_set_parent(struct clk_hw *hw, u8 index) |
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{ |
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struct clk_scu *clk = to_clk_scu(hw); |
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struct imx_sc_msg_set_clock_parent msg; |
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struct imx_sc_rpc_msg *hdr = &msg.hdr; |
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hdr->ver = IMX_SC_RPC_VERSION; |
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hdr->svc = IMX_SC_RPC_SVC_PM; |
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hdr->func = IMX_SC_PM_FUNC_SET_CLOCK_PARENT; |
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hdr->size = 2; |
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msg.resource = cpu_to_le16(clk->rsrc_id); |
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msg.clk = clk->clk_type; |
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msg.parent = index; |
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return imx_scu_call_rpc(ccm_ipc_handle, &msg, true); |
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} |
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static int sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource, |
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u8 clk, bool enable, bool autog) |
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{ |
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struct imx_sc_msg_req_clock_enable msg; |
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struct imx_sc_rpc_msg *hdr = &msg.hdr; |
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hdr->ver = IMX_SC_RPC_VERSION; |
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hdr->svc = IMX_SC_RPC_SVC_PM; |
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hdr->func = IMX_SC_PM_FUNC_CLOCK_ENABLE; |
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hdr->size = 3; |
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msg.resource = cpu_to_le16(resource); |
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msg.clk = clk; |
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msg.enable = enable; |
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msg.autog = autog; |
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return imx_scu_call_rpc(ccm_ipc_handle, &msg, true); |
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} |
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/* |
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* clk_scu_prepare - Enable a SCU clock |
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* @hw: clock to enable |
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* |
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* Enable the clock at the DSC slice level |
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*/ |
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static int clk_scu_prepare(struct clk_hw *hw) |
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{ |
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struct clk_scu *clk = to_clk_scu(hw); |
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return sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id, |
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clk->clk_type, true, false); |
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} |
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/* |
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* clk_scu_unprepare - Disable a SCU clock |
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* @hw: clock to enable |
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* |
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* Disable the clock at the DSC slice level |
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*/ |
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static void clk_scu_unprepare(struct clk_hw *hw) |
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{ |
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struct clk_scu *clk = to_clk_scu(hw); |
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int ret; |
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ret = sc_pm_clock_enable(ccm_ipc_handle, clk->rsrc_id, |
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clk->clk_type, false, false); |
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if (ret) |
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pr_warn("%s: clk unprepare failed %d\n", clk_hw_get_name(hw), |
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ret); |
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} |
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static const struct clk_ops clk_scu_ops = { |
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.recalc_rate = clk_scu_recalc_rate, |
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.round_rate = clk_scu_round_rate, |
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.set_rate = clk_scu_set_rate, |
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.get_parent = clk_scu_get_parent, |
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.set_parent = clk_scu_set_parent, |
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.prepare = clk_scu_prepare, |
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.unprepare = clk_scu_unprepare, |
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}; |
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static const struct clk_ops clk_scu_cpu_ops = { |
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.recalc_rate = clk_scu_recalc_rate, |
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.round_rate = clk_scu_round_rate, |
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.set_rate = clk_scu_atf_set_cpu_rate, |
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.prepare = clk_scu_prepare, |
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.unprepare = clk_scu_unprepare, |
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}; |
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struct clk_hw *__imx_clk_scu(struct device *dev, const char *name, |
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const char * const *parents, int num_parents, |
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u32 rsrc_id, u8 clk_type) |
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{ |
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struct clk_init_data init; |
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struct clk_scu *clk; |
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struct clk_hw *hw; |
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int ret; |
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clk = kzalloc(sizeof(*clk), GFP_KERNEL); |
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if (!clk) |
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return ERR_PTR(-ENOMEM); |
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clk->rsrc_id = rsrc_id; |
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clk->clk_type = clk_type; |
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init.name = name; |
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init.ops = &clk_scu_ops; |
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if (rsrc_id == IMX_SC_R_A35) |
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init.ops = &clk_scu_cpu_ops; |
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else |
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init.ops = &clk_scu_ops; |
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init.parent_names = parents; |
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init.num_parents = num_parents; |
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/* |
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* Note on MX8, the clocks are tightly coupled with power domain |
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* that once the power domain is off, the clock status may be |
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* lost. So we make it NOCACHE to let user to retrieve the real |
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* clock status from HW instead of using the possible invalid |
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* cached rate. |
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*/ |
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init.flags = CLK_GET_RATE_NOCACHE; |
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clk->hw.init = &init; |
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hw = &clk->hw; |
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ret = clk_hw_register(dev, hw); |
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if (ret) { |
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kfree(clk); |
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hw = ERR_PTR(ret); |
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} |
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if (dev) |
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dev_set_drvdata(dev, clk); |
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return hw; |
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} |
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struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec, |
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void *data) |
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{ |
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unsigned int rsrc = clkspec->args[0]; |
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unsigned int idx = clkspec->args[1]; |
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struct list_head *scu_clks = data; |
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struct imx_scu_clk_node *clk; |
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list_for_each_entry(clk, &scu_clks[rsrc], node) { |
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if (clk->clk_type == idx) |
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return clk->hw; |
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} |
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return ERR_PTR(-ENODEV); |
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} |
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static int imx_clk_scu_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct imx_scu_clk_node *clk = dev_get_platdata(dev); |
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struct clk_hw *hw; |
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int ret; |
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pm_runtime_set_suspended(dev); |
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pm_runtime_set_autosuspend_delay(dev, 50); |
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pm_runtime_use_autosuspend(&pdev->dev); |
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pm_runtime_enable(dev); |
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ret = pm_runtime_get_sync(dev); |
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if (ret) { |
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pm_runtime_disable(dev); |
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return ret; |
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} |
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hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents, |
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clk->rsrc, clk->clk_type); |
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if (IS_ERR(hw)) { |
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pm_runtime_disable(dev); |
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return PTR_ERR(hw); |
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} |
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clk->hw = hw; |
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list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]); |
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pm_runtime_mark_last_busy(&pdev->dev); |
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pm_runtime_put_autosuspend(&pdev->dev); |
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dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc, |
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clk->clk_type); |
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return 0; |
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} |
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static int __maybe_unused imx_clk_scu_suspend(struct device *dev) |
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{ |
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struct clk_scu *clk = dev_get_drvdata(dev); |
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clk->rate = clk_hw_get_rate(&clk->hw); |
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clk->is_enabled = clk_hw_is_enabled(&clk->hw); |
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if (clk->rate) |
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dev_dbg(dev, "save rate %d\n", clk->rate); |
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if (clk->is_enabled) |
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dev_dbg(dev, "save enabled state\n"); |
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return 0; |
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} |
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static int __maybe_unused imx_clk_scu_resume(struct device *dev) |
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{ |
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struct clk_scu *clk = dev_get_drvdata(dev); |
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int ret = 0; |
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if (clk->rate) { |
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ret = clk_scu_set_rate(&clk->hw, clk->rate, 0); |
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dev_dbg(dev, "restore rate %d %s\n", clk->rate, |
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!ret ? "success" : "failed"); |
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} |
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if (clk->is_enabled) { |
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ret = clk_scu_prepare(&clk->hw); |
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dev_dbg(dev, "restore enabled state %s\n", |
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!ret ? "success" : "failed"); |
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} |
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return ret; |
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} |
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static const struct dev_pm_ops imx_clk_scu_pm_ops = { |
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_clk_scu_suspend, |
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imx_clk_scu_resume) |
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}; |
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static struct platform_driver imx_clk_scu_driver = { |
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.driver = { |
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.name = "imx-scu-clk", |
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.suppress_bind_attrs = true, |
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.pm = &imx_clk_scu_pm_ops, |
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}, |
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.probe = imx_clk_scu_probe, |
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}; |
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static int imx_clk_scu_attach_pd(struct device *dev, u32 rsrc_id) |
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{ |
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struct of_phandle_args genpdspec = { |
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.np = pd_np, |
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.args_count = 1, |
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.args[0] = rsrc_id, |
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}; |
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if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53 || |
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rsrc_id == IMX_SC_R_A72) |
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return 0; |
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return of_genpd_add_device(&genpdspec, dev); |
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} |
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struct clk_hw *imx_clk_scu_alloc_dev(const char *name, |
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const char * const *parents, |
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int num_parents, u32 rsrc_id, u8 clk_type) |
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{ |
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struct imx_scu_clk_node clk = { |
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.name = name, |
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.rsrc = rsrc_id, |
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.clk_type = clk_type, |
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.parents = parents, |
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.num_parents = num_parents, |
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}; |
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struct platform_device *pdev; |
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int ret; |
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pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE); |
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if (!pdev) { |
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pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n", |
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name, rsrc_id, clk_type); |
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return ERR_PTR(-ENOMEM); |
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} |
|
|
|
ret = platform_device_add_data(pdev, &clk, sizeof(clk)); |
|
if (ret) { |
|
platform_device_put(pdev); |
|
return ERR_PTR(ret); |
|
} |
|
|
|
pdev->driver_override = "imx-scu-clk"; |
|
|
|
ret = imx_clk_scu_attach_pd(&pdev->dev, rsrc_id); |
|
if (ret) |
|
pr_warn("%s: failed to attached the power domain %d\n", |
|
name, ret); |
|
|
|
platform_device_add(pdev); |
|
|
|
/* For API backwards compatiblilty, simply return NULL for success */ |
|
return NULL; |
|
} |
|
|
|
void imx_clk_scu_unregister(void) |
|
{ |
|
struct imx_scu_clk_node *clk; |
|
int i; |
|
|
|
for (i = 0; i < IMX_SC_R_LAST; i++) { |
|
list_for_each_entry(clk, &imx_scu_clks[i], node) { |
|
clk_hw_unregister(clk->hw); |
|
kfree(clk); |
|
} |
|
} |
|
}
|
|
|