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272 lines
6.4 KiB
272 lines
6.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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#include <linux/kernel.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/errno.h> |
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#include <linux/delay.h> |
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#include <linux/slab.h> |
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#include <linux/err.h> |
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#include <asm/div64.h> |
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#include "clk.h" |
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#define to_clk_pllv2(clk) (container_of(clk, struct clk_pllv2, clk)) |
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/* PLL Register Offsets */ |
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#define MXC_PLL_DP_CTL 0x00 |
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#define MXC_PLL_DP_CONFIG 0x04 |
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#define MXC_PLL_DP_OP 0x08 |
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#define MXC_PLL_DP_MFD 0x0C |
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#define MXC_PLL_DP_MFN 0x10 |
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#define MXC_PLL_DP_MFNMINUS 0x14 |
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#define MXC_PLL_DP_MFNPLUS 0x18 |
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#define MXC_PLL_DP_HFS_OP 0x1C |
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#define MXC_PLL_DP_HFS_MFD 0x20 |
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#define MXC_PLL_DP_HFS_MFN 0x24 |
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#define MXC_PLL_DP_MFN_TOGC 0x28 |
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#define MXC_PLL_DP_DESTAT 0x2c |
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/* PLL Register Bit definitions */ |
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#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 |
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#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 |
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#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 |
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#define MXC_PLL_DP_CTL_ADE 0x800 |
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#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 |
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#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) |
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#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 |
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#define MXC_PLL_DP_CTL_HFSM 0x80 |
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#define MXC_PLL_DP_CTL_PRE 0x40 |
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#define MXC_PLL_DP_CTL_UPEN 0x20 |
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#define MXC_PLL_DP_CTL_RST 0x10 |
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#define MXC_PLL_DP_CTL_RCP 0x8 |
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#define MXC_PLL_DP_CTL_PLM 0x4 |
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#define MXC_PLL_DP_CTL_BRM0 0x2 |
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#define MXC_PLL_DP_CTL_LRF 0x1 |
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#define MXC_PLL_DP_CONFIG_BIST 0x8 |
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#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 |
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#define MXC_PLL_DP_CONFIG_AREN 0x2 |
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#define MXC_PLL_DP_CONFIG_LDREQ 0x1 |
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#define MXC_PLL_DP_OP_MFI_OFFSET 4 |
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#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) |
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#define MXC_PLL_DP_OP_PDF_OFFSET 0 |
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#define MXC_PLL_DP_OP_PDF_MASK 0xF |
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#define MXC_PLL_DP_MFD_OFFSET 0 |
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#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF |
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#define MXC_PLL_DP_MFN_OFFSET 0x0 |
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#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF |
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#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) |
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#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) |
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#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 |
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#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF |
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#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) |
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#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF |
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#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ |
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struct clk_pllv2 { |
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struct clk_hw hw; |
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void __iomem *base; |
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}; |
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static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate, |
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u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn) |
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{ |
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long mfi, mfn, mfd, pdf, ref_clk; |
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unsigned long dbl; |
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u64 temp; |
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dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; |
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pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; |
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mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; |
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mfi = (mfi <= 5) ? 5 : mfi; |
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mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; |
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mfn = dp_mfn & MXC_PLL_DP_MFN_MASK; |
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mfn = sign_extend32(mfn, 26); |
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ref_clk = 2 * parent_rate; |
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if (dbl != 0) |
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ref_clk *= 2; |
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ref_clk /= (pdf + 1); |
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temp = (u64) ref_clk * abs(mfn); |
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do_div(temp, mfd + 1); |
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if (mfn < 0) |
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temp = (ref_clk * mfi) - temp; |
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else |
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temp = (ref_clk * mfi) + temp; |
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return temp; |
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} |
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static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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u32 dp_op, dp_mfd, dp_mfn, dp_ctl; |
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void __iomem *pllbase; |
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struct clk_pllv2 *pll = to_clk_pllv2(hw); |
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pllbase = pll->base; |
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dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); |
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dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); |
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dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); |
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dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); |
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return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn); |
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} |
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static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate, |
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u32 *dp_op, u32 *dp_mfd, u32 *dp_mfn) |
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{ |
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u32 reg; |
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long mfi, pdf, mfn, mfd = 999999; |
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u64 temp64; |
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unsigned long quad_parent_rate; |
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quad_parent_rate = 4 * parent_rate; |
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pdf = mfi = -1; |
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while (++pdf < 16 && mfi < 5) |
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mfi = rate * (pdf+1) / quad_parent_rate; |
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if (mfi > 15) |
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return -EINVAL; |
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pdf--; |
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temp64 = rate * (pdf + 1) - quad_parent_rate * mfi; |
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do_div(temp64, quad_parent_rate / 1000000); |
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mfn = (long)temp64; |
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reg = mfi << 4 | pdf; |
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*dp_op = reg; |
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*dp_mfd = mfd; |
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*dp_mfn = mfn; |
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return 0; |
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} |
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static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct clk_pllv2 *pll = to_clk_pllv2(hw); |
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void __iomem *pllbase; |
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u32 dp_ctl, dp_op, dp_mfd, dp_mfn; |
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int ret; |
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pllbase = pll->base; |
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ret = __clk_pllv2_set_rate(rate, parent_rate, &dp_op, &dp_mfd, &dp_mfn); |
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if (ret) |
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return ret; |
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dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); |
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/* use dpdck0_2 */ |
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__raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); |
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__raw_writel(dp_op, pllbase + MXC_PLL_DP_OP); |
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__raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD); |
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__raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN); |
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return 0; |
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} |
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static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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u32 dp_op, dp_mfd, dp_mfn; |
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int ret; |
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ret = __clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn); |
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if (ret) |
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return ret; |
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return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN, |
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dp_op, dp_mfd, dp_mfn); |
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} |
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static int clk_pllv2_prepare(struct clk_hw *hw) |
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{ |
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struct clk_pllv2 *pll = to_clk_pllv2(hw); |
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u32 reg; |
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void __iomem *pllbase; |
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int i = 0; |
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pllbase = pll->base; |
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reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; |
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__raw_writel(reg, pllbase + MXC_PLL_DP_CTL); |
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/* Wait for lock */ |
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do { |
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reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); |
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if (reg & MXC_PLL_DP_CTL_LRF) |
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break; |
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udelay(1); |
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} while (++i < MAX_DPLL_WAIT_TRIES); |
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if (i == MAX_DPLL_WAIT_TRIES) { |
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pr_err("MX5: pll locking failed\n"); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static void clk_pllv2_unprepare(struct clk_hw *hw) |
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{ |
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struct clk_pllv2 *pll = to_clk_pllv2(hw); |
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u32 reg; |
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void __iomem *pllbase; |
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pllbase = pll->base; |
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reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; |
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__raw_writel(reg, pllbase + MXC_PLL_DP_CTL); |
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} |
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static const struct clk_ops clk_pllv2_ops = { |
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.prepare = clk_pllv2_prepare, |
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.unprepare = clk_pllv2_unprepare, |
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.recalc_rate = clk_pllv2_recalc_rate, |
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.round_rate = clk_pllv2_round_rate, |
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.set_rate = clk_pllv2_set_rate, |
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}; |
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struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent, |
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void __iomem *base) |
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{ |
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struct clk_pllv2 *pll; |
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struct clk_hw *hw; |
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struct clk_init_data init; |
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int ret; |
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pll = kzalloc(sizeof(*pll), GFP_KERNEL); |
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if (!pll) |
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return ERR_PTR(-ENOMEM); |
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pll->base = base; |
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init.name = name; |
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init.ops = &clk_pllv2_ops; |
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init.flags = 0; |
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init.parent_names = &parent; |
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init.num_parents = 1; |
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pll->hw.init = &init; |
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hw = &pll->hw; |
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ret = clk_hw_register(NULL, hw); |
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if (ret) { |
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kfree(pll); |
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return ERR_PTR(ret); |
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} |
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return hw; |
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}
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