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229 lines
4.6 KiB
229 lines
4.6 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2016 Freescale Semiconductor, Inc. |
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* Copyright 2017~2018 NXP |
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* |
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* Author: Dong Aisheng <[email protected]> |
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* |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/slab.h> |
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#include "clk.h" |
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/** |
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* struct clk_pfdv2 - IMX PFD clock |
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* @hw: clock source |
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* @reg: PFD register address |
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* @gate_bit: Gate bit offset |
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* @vld_bit: Valid bit offset |
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* @frac_off: PLL Fractional Divider offset |
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*/ |
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struct clk_pfdv2 { |
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struct clk_hw hw; |
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void __iomem *reg; |
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u8 gate_bit; |
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u8 vld_bit; |
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u8 frac_off; |
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}; |
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#define to_clk_pfdv2(_hw) container_of(_hw, struct clk_pfdv2, hw) |
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#define CLK_PFDV2_FRAC_MASK 0x3f |
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#define LOCK_TIMEOUT_US USEC_PER_MSEC |
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static DEFINE_SPINLOCK(pfd_lock); |
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static int clk_pfdv2_wait(struct clk_pfdv2 *pfd) |
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{ |
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u32 val; |
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return readl_poll_timeout(pfd->reg, val, val & (1 << pfd->vld_bit), |
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0, LOCK_TIMEOUT_US); |
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} |
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static int clk_pfdv2_enable(struct clk_hw *hw) |
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{ |
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struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); |
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unsigned long flags; |
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u32 val; |
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spin_lock_irqsave(&pfd_lock, flags); |
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val = readl_relaxed(pfd->reg); |
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val &= ~(1 << pfd->gate_bit); |
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writel_relaxed(val, pfd->reg); |
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spin_unlock_irqrestore(&pfd_lock, flags); |
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return clk_pfdv2_wait(pfd); |
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} |
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static void clk_pfdv2_disable(struct clk_hw *hw) |
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{ |
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struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); |
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unsigned long flags; |
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u32 val; |
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spin_lock_irqsave(&pfd_lock, flags); |
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val = readl_relaxed(pfd->reg); |
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val |= (1 << pfd->gate_bit); |
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writel_relaxed(val, pfd->reg); |
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spin_unlock_irqrestore(&pfd_lock, flags); |
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} |
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static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); |
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u64 tmp = parent_rate; |
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u8 frac; |
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frac = (readl_relaxed(pfd->reg) >> pfd->frac_off) |
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& CLK_PFDV2_FRAC_MASK; |
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if (!frac) { |
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pr_debug("clk_pfdv2: %s invalid pfd frac value 0\n", |
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clk_hw_get_name(hw)); |
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return 0; |
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} |
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tmp *= 18; |
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do_div(tmp, frac); |
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return tmp; |
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} |
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static int clk_pfdv2_determine_rate(struct clk_hw *hw, |
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struct clk_rate_request *req) |
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{ |
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unsigned long parent_rates[] = { |
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480000000, |
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528000000, |
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req->best_parent_rate |
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}; |
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unsigned long best_rate = -1UL, rate = req->rate; |
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unsigned long best_parent_rate = req->best_parent_rate; |
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u64 tmp; |
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u8 frac; |
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int i; |
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for (i = 0; i < ARRAY_SIZE(parent_rates); i++) { |
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tmp = parent_rates[i]; |
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tmp = tmp * 18 + rate / 2; |
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do_div(tmp, rate); |
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frac = tmp; |
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if (frac < 12) |
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frac = 12; |
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else if (frac > 35) |
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frac = 35; |
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tmp = parent_rates[i]; |
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tmp *= 18; |
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do_div(tmp, frac); |
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if (abs(tmp - req->rate) < abs(best_rate - req->rate)) { |
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best_rate = tmp; |
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best_parent_rate = parent_rates[i]; |
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} |
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} |
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req->best_parent_rate = best_parent_rate; |
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req->rate = best_rate; |
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return 0; |
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} |
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static int clk_pfdv2_is_enabled(struct clk_hw *hw) |
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{ |
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struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); |
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if (readl_relaxed(pfd->reg) & (1 << pfd->gate_bit)) |
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return 0; |
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return 1; |
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} |
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static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct clk_pfdv2 *pfd = to_clk_pfdv2(hw); |
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unsigned long flags; |
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u64 tmp = parent_rate; |
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u32 val; |
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u8 frac; |
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if (!rate) |
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return -EINVAL; |
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/* PFD can NOT change rate without gating */ |
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WARN_ON(clk_pfdv2_is_enabled(hw)); |
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tmp = tmp * 18 + rate / 2; |
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do_div(tmp, rate); |
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frac = tmp; |
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if (frac < 12) |
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frac = 12; |
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else if (frac > 35) |
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frac = 35; |
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spin_lock_irqsave(&pfd_lock, flags); |
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val = readl_relaxed(pfd->reg); |
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val &= ~(CLK_PFDV2_FRAC_MASK << pfd->frac_off); |
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val |= frac << pfd->frac_off; |
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writel_relaxed(val, pfd->reg); |
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spin_unlock_irqrestore(&pfd_lock, flags); |
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return 0; |
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} |
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static const struct clk_ops clk_pfdv2_ops = { |
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.enable = clk_pfdv2_enable, |
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.disable = clk_pfdv2_disable, |
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.recalc_rate = clk_pfdv2_recalc_rate, |
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.determine_rate = clk_pfdv2_determine_rate, |
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.set_rate = clk_pfdv2_set_rate, |
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.is_enabled = clk_pfdv2_is_enabled, |
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}; |
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struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name, |
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void __iomem *reg, u8 idx) |
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{ |
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struct clk_init_data init; |
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struct clk_pfdv2 *pfd; |
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struct clk_hw *hw; |
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int ret; |
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WARN_ON(idx > 3); |
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pfd = kzalloc(sizeof(*pfd), GFP_KERNEL); |
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if (!pfd) |
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return ERR_PTR(-ENOMEM); |
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pfd->reg = reg; |
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pfd->gate_bit = (idx + 1) * 8 - 1; |
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pfd->vld_bit = pfd->gate_bit - 1; |
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pfd->frac_off = idx * 8; |
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init.name = name; |
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init.ops = &clk_pfdv2_ops; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT; |
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pfd->hw.init = &init; |
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hw = &pfd->hw; |
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ret = clk_hw_register(NULL, hw); |
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if (ret) { |
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kfree(pfd); |
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hw = ERR_PTR(ret); |
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} |
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return hw; |
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}
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