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162 lines
3.4 KiB
162 lines
3.4 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright 2018 NXP |
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* Dong Aisheng <[email protected]> |
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*/ |
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#include <linux/bits.h> |
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#include <linux/clk-provider.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include "clk-scu.h" |
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static DEFINE_SPINLOCK(imx_lpcg_scu_lock); |
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#define CLK_GATE_SCU_LPCG_MASK 0x3 |
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#define CLK_GATE_SCU_LPCG_HW_SEL BIT(0) |
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#define CLK_GATE_SCU_LPCG_SW_SEL BIT(1) |
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/* |
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* struct clk_lpcg_scu - Description of LPCG clock |
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* |
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* @hw: clk_hw of this LPCG |
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* @reg: register of this LPCG clock |
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* @bit_idx: bit index of this LPCG clock |
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* @hw_gate: HW auto gate enable |
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* |
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* This structure describes one LPCG clock |
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*/ |
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struct clk_lpcg_scu { |
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struct clk_hw hw; |
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void __iomem *reg; |
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u8 bit_idx; |
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bool hw_gate; |
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/* for state save&restore */ |
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u32 state; |
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}; |
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#define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw) |
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static int clk_lpcg_scu_enable(struct clk_hw *hw) |
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{ |
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struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); |
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unsigned long flags; |
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u32 reg, val; |
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spin_lock_irqsave(&imx_lpcg_scu_lock, flags); |
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reg = readl_relaxed(clk->reg); |
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reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); |
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val = CLK_GATE_SCU_LPCG_SW_SEL; |
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if (clk->hw_gate) |
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val |= CLK_GATE_SCU_LPCG_HW_SEL; |
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reg |= val << clk->bit_idx; |
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writel(reg, clk->reg); |
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spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); |
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return 0; |
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} |
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static void clk_lpcg_scu_disable(struct clk_hw *hw) |
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{ |
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struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); |
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unsigned long flags; |
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u32 reg; |
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spin_lock_irqsave(&imx_lpcg_scu_lock, flags); |
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reg = readl_relaxed(clk->reg); |
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reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); |
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writel(reg, clk->reg); |
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spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags); |
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} |
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static const struct clk_ops clk_lpcg_scu_ops = { |
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.enable = clk_lpcg_scu_enable, |
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.disable = clk_lpcg_scu_disable, |
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}; |
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struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name, |
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const char *parent_name, unsigned long flags, |
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void __iomem *reg, u8 bit_idx, bool hw_gate) |
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{ |
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struct clk_lpcg_scu *clk; |
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struct clk_init_data init; |
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struct clk_hw *hw; |
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int ret; |
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clk = kzalloc(sizeof(*clk), GFP_KERNEL); |
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if (!clk) |
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return ERR_PTR(-ENOMEM); |
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clk->reg = reg; |
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clk->bit_idx = bit_idx; |
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clk->hw_gate = hw_gate; |
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init.name = name; |
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init.ops = &clk_lpcg_scu_ops; |
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init.flags = CLK_SET_RATE_PARENT | flags; |
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init.parent_names = parent_name ? &parent_name : NULL; |
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init.num_parents = parent_name ? 1 : 0; |
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clk->hw.init = &init; |
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hw = &clk->hw; |
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ret = clk_hw_register(dev, hw); |
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if (ret) { |
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kfree(clk); |
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hw = ERR_PTR(ret); |
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} |
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if (dev) |
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dev_set_drvdata(dev, clk); |
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return hw; |
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} |
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void imx_clk_lpcg_scu_unregister(struct clk_hw *hw) |
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{ |
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struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw); |
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clk_hw_unregister(&clk->hw); |
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kfree(clk); |
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} |
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static int __maybe_unused imx_clk_lpcg_scu_suspend(struct device *dev) |
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{ |
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struct clk_lpcg_scu *clk = dev_get_drvdata(dev); |
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clk->state = readl_relaxed(clk->reg); |
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dev_dbg(dev, "save lpcg state 0x%x\n", clk->state); |
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return 0; |
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} |
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static int __maybe_unused imx_clk_lpcg_scu_resume(struct device *dev) |
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{ |
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struct clk_lpcg_scu *clk = dev_get_drvdata(dev); |
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/* |
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* FIXME: Sometimes writes don't work unless the CPU issues |
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* them twice |
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*/ |
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writel(clk->state, clk->reg); |
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writel(clk->state, clk->reg); |
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dev_dbg(dev, "restore lpcg state 0x%x\n", clk->state); |
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return 0; |
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} |
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const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops = { |
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_clk_lpcg_scu_suspend, |
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imx_clk_lpcg_scu_resume) |
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};
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