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237 lines
5.4 KiB
237 lines
5.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright 2018 NXP. |
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* |
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* This driver supports the fractional plls found in the imx8m SOCs |
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* |
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* Documentation for this fractional pll can be found at: |
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* https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834 |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/err.h> |
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#include <linux/export.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/slab.h> |
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#include <linux/bitfield.h> |
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#include "clk.h" |
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#define PLL_CFG0 0x0 |
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#define PLL_CFG1 0x4 |
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#define PLL_LOCK_STATUS BIT(31) |
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#define PLL_PD_MASK BIT(19) |
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#define PLL_BYPASS_MASK BIT(14) |
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#define PLL_NEWDIV_VAL BIT(12) |
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#define PLL_NEWDIV_ACK BIT(11) |
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#define PLL_FRAC_DIV_MASK GENMASK(30, 7) |
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#define PLL_INT_DIV_MASK GENMASK(6, 0) |
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#define PLL_OUTPUT_DIV_MASK GENMASK(4, 0) |
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#define PLL_FRAC_DENOM 0x1000000 |
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#define PLL_FRAC_LOCK_TIMEOUT 10000 |
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#define PLL_FRAC_ACK_TIMEOUT 500000 |
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struct clk_frac_pll { |
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struct clk_hw hw; |
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void __iomem *base; |
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}; |
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#define to_clk_frac_pll(_hw) container_of(_hw, struct clk_frac_pll, hw) |
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static int clk_wait_lock(struct clk_frac_pll *pll) |
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{ |
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u32 val; |
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return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0, |
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PLL_FRAC_LOCK_TIMEOUT); |
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} |
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static int clk_wait_ack(struct clk_frac_pll *pll) |
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{ |
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u32 val; |
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/* return directly if the pll is in powerdown or in bypass */ |
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if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK)) |
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return 0; |
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/* Wait for the pll's divfi and divff to be reloaded */ |
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return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0, |
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PLL_FRAC_ACK_TIMEOUT); |
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} |
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static int clk_pll_prepare(struct clk_hw *hw) |
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{ |
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struct clk_frac_pll *pll = to_clk_frac_pll(hw); |
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u32 val; |
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val = readl_relaxed(pll->base + PLL_CFG0); |
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val &= ~PLL_PD_MASK; |
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writel_relaxed(val, pll->base + PLL_CFG0); |
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return clk_wait_lock(pll); |
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} |
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static void clk_pll_unprepare(struct clk_hw *hw) |
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{ |
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struct clk_frac_pll *pll = to_clk_frac_pll(hw); |
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u32 val; |
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val = readl_relaxed(pll->base + PLL_CFG0); |
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val |= PLL_PD_MASK; |
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writel_relaxed(val, pll->base + PLL_CFG0); |
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} |
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static int clk_pll_is_prepared(struct clk_hw *hw) |
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{ |
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struct clk_frac_pll *pll = to_clk_frac_pll(hw); |
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u32 val; |
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val = readl_relaxed(pll->base + PLL_CFG0); |
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return (val & PLL_PD_MASK) ? 0 : 1; |
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} |
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static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_frac_pll *pll = to_clk_frac_pll(hw); |
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u32 val, divff, divfi, divq; |
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u64 temp64 = parent_rate; |
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u64 rate; |
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val = readl_relaxed(pll->base + PLL_CFG0); |
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divq = (FIELD_GET(PLL_OUTPUT_DIV_MASK, val) + 1) * 2; |
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val = readl_relaxed(pll->base + PLL_CFG1); |
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divff = FIELD_GET(PLL_FRAC_DIV_MASK, val); |
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divfi = FIELD_GET(PLL_INT_DIV_MASK, val); |
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temp64 *= 8; |
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temp64 *= divff; |
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do_div(temp64, PLL_FRAC_DENOM); |
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do_div(temp64, divq); |
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rate = parent_rate * 8 * (divfi + 1); |
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do_div(rate, divq); |
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rate += temp64; |
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return rate; |
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} |
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static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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u64 parent_rate = *prate; |
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u32 divff, divfi; |
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u64 temp64; |
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parent_rate *= 8; |
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rate *= 2; |
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temp64 = rate; |
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do_div(temp64, parent_rate); |
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divfi = temp64; |
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temp64 = rate - divfi * parent_rate; |
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temp64 *= PLL_FRAC_DENOM; |
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do_div(temp64, parent_rate); |
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divff = temp64; |
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temp64 = parent_rate; |
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temp64 *= divff; |
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do_div(temp64, PLL_FRAC_DENOM); |
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rate = parent_rate * divfi + temp64; |
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return rate / 2; |
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} |
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/* |
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* To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero |
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* (means the PLL output will be divided by 2). So the PLL output can use |
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* the below formula: |
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* pllout = parent_rate * 8 / 2 * DIVF_VAL; |
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* where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24. |
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*/ |
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static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct clk_frac_pll *pll = to_clk_frac_pll(hw); |
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u32 val, divfi, divff; |
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u64 temp64; |
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int ret; |
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parent_rate *= 8; |
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rate *= 2; |
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divfi = rate / parent_rate; |
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temp64 = parent_rate * divfi; |
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temp64 = rate - temp64; |
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temp64 *= PLL_FRAC_DENOM; |
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do_div(temp64, parent_rate); |
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divff = temp64; |
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val = readl_relaxed(pll->base + PLL_CFG1); |
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val &= ~(PLL_FRAC_DIV_MASK | PLL_INT_DIV_MASK); |
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val |= (divff << 7) | (divfi - 1); |
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writel_relaxed(val, pll->base + PLL_CFG1); |
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val = readl_relaxed(pll->base + PLL_CFG0); |
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val &= ~0x1f; |
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writel_relaxed(val, pll->base + PLL_CFG0); |
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/* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */ |
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val = readl_relaxed(pll->base + PLL_CFG0); |
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val |= PLL_NEWDIV_VAL; |
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writel_relaxed(val, pll->base + PLL_CFG0); |
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ret = clk_wait_ack(pll); |
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/* clear the NEV_DIV_VAL */ |
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val = readl_relaxed(pll->base + PLL_CFG0); |
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val &= ~PLL_NEWDIV_VAL; |
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writel_relaxed(val, pll->base + PLL_CFG0); |
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return ret; |
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} |
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static const struct clk_ops clk_frac_pll_ops = { |
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.prepare = clk_pll_prepare, |
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.unprepare = clk_pll_unprepare, |
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.is_prepared = clk_pll_is_prepared, |
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.recalc_rate = clk_pll_recalc_rate, |
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.round_rate = clk_pll_round_rate, |
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.set_rate = clk_pll_set_rate, |
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}; |
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struct clk_hw *imx_clk_hw_frac_pll(const char *name, |
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const char *parent_name, |
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void __iomem *base) |
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{ |
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struct clk_init_data init; |
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struct clk_frac_pll *pll; |
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struct clk_hw *hw; |
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int ret; |
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pll = kzalloc(sizeof(*pll), GFP_KERNEL); |
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if (!pll) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &clk_frac_pll_ops; |
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init.flags = 0; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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pll->base = base; |
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pll->hw.init = &init; |
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hw = &pll->hw; |
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ret = clk_hw_register(NULL, hw); |
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if (ret) { |
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kfree(pll); |
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return ERR_PTR(ret); |
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} |
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return hw; |
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} |
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EXPORT_SYMBOL_GPL(imx_clk_hw_frac_pll);
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