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575 lines
14 KiB
575 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Clock driver for TI Davinci PSC controllers |
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* |
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* Copyright (C) 2017 David Lechner <[email protected]> |
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* |
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* Based on: drivers/clk/keystone/gate.c |
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* Copyright (C) 2013 Texas Instruments. |
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* Murali Karicheri <[email protected]> |
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* Santosh Shilimkar <[email protected]> |
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* |
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* And: arch/arm/mach-davinci/psc.c |
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* Copyright (C) 2006 Texas Instruments. |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/clk.h> |
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#include <linux/clk/davinci.h> |
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#include <linux/clkdev.h> |
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#include <linux/err.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_clock.h> |
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#include <linux/pm_domain.h> |
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#include <linux/regmap.h> |
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#include <linux/reset-controller.h> |
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#include <linux/slab.h> |
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#include <linux/types.h> |
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#include "psc.h" |
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/* PSC register offsets */ |
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#define EPCPR 0x070 |
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#define PTCMD 0x120 |
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#define PTSTAT 0x128 |
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#define PDSTAT(n) (0x200 + 4 * (n)) |
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#define PDCTL(n) (0x300 + 4 * (n)) |
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#define MDSTAT(n) (0x800 + 4 * (n)) |
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#define MDCTL(n) (0xa00 + 4 * (n)) |
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/* PSC module states */ |
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enum davinci_lpsc_state { |
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LPSC_STATE_SWRSTDISABLE = 0, |
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LPSC_STATE_SYNCRST = 1, |
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LPSC_STATE_DISABLE = 2, |
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LPSC_STATE_ENABLE = 3, |
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}; |
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#define MDSTAT_STATE_MASK GENMASK(5, 0) |
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#define MDSTAT_MCKOUT BIT(12) |
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#define PDSTAT_STATE_MASK GENMASK(4, 0) |
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#define MDCTL_FORCE BIT(31) |
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#define MDCTL_LRESET BIT(8) |
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#define PDCTL_EPCGOOD BIT(8) |
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#define PDCTL_NEXT BIT(0) |
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struct davinci_psc_data { |
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struct clk_onecell_data clk_data; |
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struct genpd_onecell_data pm_data; |
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struct reset_controller_dev rcdev; |
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}; |
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/** |
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* struct davinci_lpsc_clk - LPSC clock structure |
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* @dev: the device that provides this LPSC or NULL |
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* @hw: clk_hw for the LPSC |
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* @pm_domain: power domain for the LPSC |
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* @genpd_clk: clock reference owned by @pm_domain |
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* @regmap: PSC MMIO region |
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* @md: Module domain (LPSC module id) |
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* @pd: Power domain |
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* @flags: LPSC_* quirk flags |
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*/ |
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struct davinci_lpsc_clk { |
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struct device *dev; |
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struct clk_hw hw; |
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struct generic_pm_domain pm_domain; |
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struct clk *genpd_clk; |
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struct regmap *regmap; |
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u32 md; |
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u32 pd; |
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u32 flags; |
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}; |
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#define to_davinci_psc_data(x) container_of(x, struct davinci_psc_data, x) |
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#define to_davinci_lpsc_clk(x) container_of(x, struct davinci_lpsc_clk, x) |
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/** |
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* best_dev_name - get the "best" device name. |
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* @dev: the device |
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* |
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* Returns the device tree compatible name if the device has a DT node, |
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* otherwise return the device name. This is mainly needed because clkdev |
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* lookups are limited to 20 chars for dev_id and when using device tree, |
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* dev_name(dev) is much longer than that. |
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*/ |
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static inline const char *best_dev_name(struct device *dev) |
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{ |
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const char *compatible; |
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if (!of_property_read_string(dev->of_node, "compatible", &compatible)) |
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return compatible; |
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return dev_name(dev); |
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} |
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static void davinci_lpsc_config(struct davinci_lpsc_clk *lpsc, |
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enum davinci_lpsc_state next_state) |
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{ |
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u32 epcpr, pdstat, mdstat, ptstat; |
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regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDSTAT_STATE_MASK, |
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next_state); |
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if (lpsc->flags & LPSC_FORCE) |
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regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_FORCE, |
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MDCTL_FORCE); |
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regmap_read(lpsc->regmap, PDSTAT(lpsc->pd), &pdstat); |
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if ((pdstat & PDSTAT_STATE_MASK) == 0) { |
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regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_NEXT, |
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PDCTL_NEXT); |
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regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd)); |
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regmap_read_poll_timeout(lpsc->regmap, EPCPR, epcpr, |
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epcpr & BIT(lpsc->pd), 0, 0); |
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regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_EPCGOOD, |
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PDCTL_EPCGOOD); |
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} else { |
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regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd)); |
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} |
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regmap_read_poll_timeout(lpsc->regmap, PTSTAT, ptstat, |
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!(ptstat & BIT(lpsc->pd)), 0, 0); |
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regmap_read_poll_timeout(lpsc->regmap, MDSTAT(lpsc->md), mdstat, |
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(mdstat & MDSTAT_STATE_MASK) == next_state, |
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0, 0); |
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} |
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static int davinci_lpsc_clk_enable(struct clk_hw *hw) |
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{ |
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struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw); |
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davinci_lpsc_config(lpsc, LPSC_STATE_ENABLE); |
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return 0; |
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} |
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static void davinci_lpsc_clk_disable(struct clk_hw *hw) |
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{ |
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struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw); |
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davinci_lpsc_config(lpsc, LPSC_STATE_DISABLE); |
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} |
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static int davinci_lpsc_clk_is_enabled(struct clk_hw *hw) |
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{ |
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struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw); |
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u32 mdstat; |
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regmap_read(lpsc->regmap, MDSTAT(lpsc->md), &mdstat); |
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return (mdstat & MDSTAT_MCKOUT) ? 1 : 0; |
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} |
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static const struct clk_ops davinci_lpsc_clk_ops = { |
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.enable = davinci_lpsc_clk_enable, |
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.disable = davinci_lpsc_clk_disable, |
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.is_enabled = davinci_lpsc_clk_is_enabled, |
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}; |
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static int davinci_psc_genpd_attach_dev(struct generic_pm_domain *pm_domain, |
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struct device *dev) |
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{ |
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struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain); |
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struct clk *clk; |
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int ret; |
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/* |
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* pm_clk_remove_clk() will call clk_put(), so we have to use clk_get() |
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* to get the clock instead of using lpsc->hw.clk directly. |
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*/ |
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clk = clk_get_sys(best_dev_name(lpsc->dev), clk_hw_get_name(&lpsc->hw)); |
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if (IS_ERR(clk)) |
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return (PTR_ERR(clk)); |
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ret = pm_clk_create(dev); |
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if (ret < 0) |
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goto fail_clk_put; |
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ret = pm_clk_add_clk(dev, clk); |
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if (ret < 0) |
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goto fail_pm_clk_destroy; |
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lpsc->genpd_clk = clk; |
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return 0; |
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fail_pm_clk_destroy: |
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pm_clk_destroy(dev); |
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fail_clk_put: |
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clk_put(clk); |
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return ret; |
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} |
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static void davinci_psc_genpd_detach_dev(struct generic_pm_domain *pm_domain, |
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struct device *dev) |
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{ |
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struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain); |
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pm_clk_remove_clk(dev, lpsc->genpd_clk); |
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pm_clk_destroy(dev); |
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lpsc->genpd_clk = NULL; |
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} |
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/** |
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* davinci_lpsc_clk_register - register LPSC clock |
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* @dev: the clocks's device or NULL |
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* @name: name of this clock |
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* @parent_name: name of clock's parent |
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* @regmap: PSC MMIO region |
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* @md: local PSC number |
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* @pd: power domain |
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* @flags: LPSC_* flags |
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*/ |
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static struct davinci_lpsc_clk * |
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davinci_lpsc_clk_register(struct device *dev, const char *name, |
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const char *parent_name, struct regmap *regmap, |
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u32 md, u32 pd, u32 flags) |
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{ |
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struct clk_init_data init; |
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struct davinci_lpsc_clk *lpsc; |
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int ret; |
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bool is_on; |
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lpsc = kzalloc(sizeof(*lpsc), GFP_KERNEL); |
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if (!lpsc) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &davinci_lpsc_clk_ops; |
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init.parent_names = (parent_name ? &parent_name : NULL); |
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init.num_parents = (parent_name ? 1 : 0); |
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init.flags = 0; |
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if (flags & LPSC_ALWAYS_ENABLED) |
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init.flags |= CLK_IS_CRITICAL; |
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if (flags & LPSC_SET_RATE_PARENT) |
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init.flags |= CLK_SET_RATE_PARENT; |
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lpsc->dev = dev; |
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lpsc->regmap = regmap; |
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lpsc->hw.init = &init; |
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lpsc->md = md; |
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lpsc->pd = pd; |
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lpsc->flags = flags; |
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ret = clk_hw_register(dev, &lpsc->hw); |
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if (ret < 0) { |
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kfree(lpsc); |
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return ERR_PTR(ret); |
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} |
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/* for now, genpd is only registered when using device-tree */ |
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if (!dev || !dev->of_node) |
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return lpsc; |
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/* genpd attach needs a way to look up this clock */ |
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ret = clk_hw_register_clkdev(&lpsc->hw, name, best_dev_name(dev)); |
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lpsc->pm_domain.name = devm_kasprintf(dev, GFP_KERNEL, "%s: %s", |
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best_dev_name(dev), name); |
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lpsc->pm_domain.attach_dev = davinci_psc_genpd_attach_dev; |
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lpsc->pm_domain.detach_dev = davinci_psc_genpd_detach_dev; |
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lpsc->pm_domain.flags = GENPD_FLAG_PM_CLK; |
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is_on = davinci_lpsc_clk_is_enabled(&lpsc->hw); |
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pm_genpd_init(&lpsc->pm_domain, NULL, is_on); |
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return lpsc; |
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} |
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static int davinci_lpsc_clk_reset(struct clk *clk, bool reset) |
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{ |
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struct clk_hw *hw = __clk_get_hw(clk); |
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struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw); |
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u32 mdctl; |
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if (IS_ERR_OR_NULL(lpsc)) |
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return -EINVAL; |
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mdctl = reset ? 0 : MDCTL_LRESET; |
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regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_LRESET, mdctl); |
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return 0; |
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} |
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static int davinci_psc_reset_assert(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct davinci_psc_data *psc = to_davinci_psc_data(rcdev); |
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struct clk *clk = psc->clk_data.clks[id]; |
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return davinci_lpsc_clk_reset(clk, true); |
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} |
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static int davinci_psc_reset_deassert(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct davinci_psc_data *psc = to_davinci_psc_data(rcdev); |
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struct clk *clk = psc->clk_data.clks[id]; |
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return davinci_lpsc_clk_reset(clk, false); |
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} |
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static const struct reset_control_ops davinci_psc_reset_ops = { |
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.assert = davinci_psc_reset_assert, |
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.deassert = davinci_psc_reset_deassert, |
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}; |
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static int davinci_psc_reset_of_xlate(struct reset_controller_dev *rcdev, |
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const struct of_phandle_args *reset_spec) |
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{ |
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struct of_phandle_args clkspec = *reset_spec; /* discard const qualifier */ |
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struct clk *clk; |
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struct clk_hw *hw; |
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struct davinci_lpsc_clk *lpsc; |
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/* the clock node is the same as the reset node */ |
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clk = of_clk_get_from_provider(&clkspec); |
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if (IS_ERR(clk)) |
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return PTR_ERR(clk); |
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hw = __clk_get_hw(clk); |
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lpsc = to_davinci_lpsc_clk(hw); |
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clk_put(clk); |
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/* not all modules support local reset */ |
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if (!(lpsc->flags & LPSC_LOCAL_RESET)) |
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return -EINVAL; |
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return lpsc->md; |
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} |
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static const struct regmap_config davinci_psc_regmap_config = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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}; |
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static struct davinci_psc_data * |
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__davinci_psc_register_clocks(struct device *dev, |
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const struct davinci_lpsc_clk_info *info, |
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int num_clks, |
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void __iomem *base) |
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{ |
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struct davinci_psc_data *psc; |
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struct clk **clks; |
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struct generic_pm_domain **pm_domains; |
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struct regmap *regmap; |
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int i, ret; |
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psc = kzalloc(sizeof(*psc), GFP_KERNEL); |
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if (!psc) |
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return ERR_PTR(-ENOMEM); |
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clks = kmalloc_array(num_clks, sizeof(*clks), GFP_KERNEL); |
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if (!clks) { |
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ret = -ENOMEM; |
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goto err_free_psc; |
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} |
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psc->clk_data.clks = clks; |
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psc->clk_data.clk_num = num_clks; |
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/* |
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* init array with error so that of_clk_src_onecell_get() doesn't |
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* return NULL for gaps in the sparse array |
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*/ |
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for (i = 0; i < num_clks; i++) |
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clks[i] = ERR_PTR(-ENOENT); |
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pm_domains = kcalloc(num_clks, sizeof(*pm_domains), GFP_KERNEL); |
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if (!pm_domains) { |
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ret = -ENOMEM; |
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goto err_free_clks; |
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} |
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psc->pm_data.domains = pm_domains; |
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psc->pm_data.num_domains = num_clks; |
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regmap = regmap_init_mmio(dev, base, &davinci_psc_regmap_config); |
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if (IS_ERR(regmap)) { |
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ret = PTR_ERR(regmap); |
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goto err_free_pm_domains; |
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} |
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for (; info->name; info++) { |
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struct davinci_lpsc_clk *lpsc; |
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lpsc = davinci_lpsc_clk_register(dev, info->name, info->parent, |
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regmap, info->md, info->pd, |
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info->flags); |
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if (IS_ERR(lpsc)) { |
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dev_warn(dev, "Failed to register %s (%ld)\n", |
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info->name, PTR_ERR(lpsc)); |
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continue; |
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} |
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clks[info->md] = lpsc->hw.clk; |
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pm_domains[info->md] = &lpsc->pm_domain; |
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} |
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/* |
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* for now, a reset controller is only registered when there is a device |
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* to associate it with. |
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*/ |
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if (!dev) |
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return psc; |
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psc->rcdev.ops = &davinci_psc_reset_ops; |
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psc->rcdev.owner = THIS_MODULE; |
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psc->rcdev.dev = dev; |
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psc->rcdev.of_node = dev->of_node; |
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psc->rcdev.of_reset_n_cells = 1; |
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psc->rcdev.of_xlate = davinci_psc_reset_of_xlate; |
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psc->rcdev.nr_resets = num_clks; |
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ret = devm_reset_controller_register(dev, &psc->rcdev); |
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if (ret < 0) |
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dev_warn(dev, "Failed to register reset controller (%d)\n", ret); |
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return psc; |
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err_free_pm_domains: |
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kfree(pm_domains); |
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err_free_clks: |
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kfree(clks); |
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err_free_psc: |
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kfree(psc); |
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return ERR_PTR(ret); |
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} |
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int davinci_psc_register_clocks(struct device *dev, |
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const struct davinci_lpsc_clk_info *info, |
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u8 num_clks, |
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void __iomem *base) |
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{ |
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struct davinci_psc_data *psc; |
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psc = __davinci_psc_register_clocks(dev, info, num_clks, base); |
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if (IS_ERR(psc)) |
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return PTR_ERR(psc); |
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for (; info->name; info++) { |
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const struct davinci_lpsc_clkdev_info *cdevs = info->cdevs; |
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struct clk *clk = psc->clk_data.clks[info->md]; |
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if (!cdevs || IS_ERR_OR_NULL(clk)) |
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continue; |
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for (; cdevs->con_id || cdevs->dev_id; cdevs++) |
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clk_register_clkdev(clk, cdevs->con_id, cdevs->dev_id); |
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} |
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return 0; |
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} |
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int of_davinci_psc_clk_init(struct device *dev, |
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const struct davinci_lpsc_clk_info *info, |
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u8 num_clks, |
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void __iomem *base) |
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{ |
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struct device_node *node = dev->of_node; |
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struct davinci_psc_data *psc; |
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psc = __davinci_psc_register_clocks(dev, info, num_clks, base); |
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if (IS_ERR(psc)) |
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return PTR_ERR(psc); |
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of_genpd_add_provider_onecell(node, &psc->pm_data); |
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of_clk_add_provider(node, of_clk_src_onecell_get, &psc->clk_data); |
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return 0; |
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} |
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static const struct of_device_id davinci_psc_of_match[] = { |
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#ifdef CONFIG_ARCH_DAVINCI_DA850 |
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{ .compatible = "ti,da850-psc0", .data = &of_da850_psc0_init_data }, |
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{ .compatible = "ti,da850-psc1", .data = &of_da850_psc1_init_data }, |
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#endif |
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{ } |
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}; |
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static const struct platform_device_id davinci_psc_id_table[] = { |
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#ifdef CONFIG_ARCH_DAVINCI_DA830 |
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{ .name = "da830-psc0", .driver_data = (kernel_ulong_t)&da830_psc0_init_data }, |
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{ .name = "da830-psc1", .driver_data = (kernel_ulong_t)&da830_psc1_init_data }, |
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#endif |
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#ifdef CONFIG_ARCH_DAVINCI_DA850 |
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{ .name = "da850-psc0", .driver_data = (kernel_ulong_t)&da850_psc0_init_data }, |
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{ .name = "da850-psc1", .driver_data = (kernel_ulong_t)&da850_psc1_init_data }, |
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#endif |
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#ifdef CONFIG_ARCH_DAVINCI_DM355 |
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{ .name = "dm355-psc", .driver_data = (kernel_ulong_t)&dm355_psc_init_data }, |
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#endif |
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#ifdef CONFIG_ARCH_DAVINCI_DM365 |
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{ .name = "dm365-psc", .driver_data = (kernel_ulong_t)&dm365_psc_init_data }, |
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#endif |
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#ifdef CONFIG_ARCH_DAVINCI_DM644x |
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{ .name = "dm644x-psc", .driver_data = (kernel_ulong_t)&dm644x_psc_init_data }, |
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#endif |
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#ifdef CONFIG_ARCH_DAVINCI_DM646x |
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{ .name = "dm646x-psc", .driver_data = (kernel_ulong_t)&dm646x_psc_init_data }, |
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#endif |
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{ } |
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}; |
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static int davinci_psc_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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const struct of_device_id *of_id; |
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const struct davinci_psc_init_data *init_data = NULL; |
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void __iomem *base; |
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int ret; |
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of_id = of_match_device(davinci_psc_of_match, dev); |
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if (of_id) |
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init_data = of_id->data; |
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else if (pdev->id_entry) |
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init_data = (void *)pdev->id_entry->driver_data; |
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if (!init_data) { |
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dev_err(dev, "unable to find driver init data\n"); |
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return -EINVAL; |
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} |
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base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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ret = devm_clk_bulk_get(dev, init_data->num_parent_clks, |
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init_data->parent_clks); |
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if (ret < 0) |
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return ret; |
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return init_data->psc_init(dev, base); |
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} |
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static struct platform_driver davinci_psc_driver = { |
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.probe = davinci_psc_probe, |
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.driver = { |
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.name = "davinci-psc-clk", |
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.of_match_table = davinci_psc_of_match, |
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}, |
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.id_table = davinci_psc_id_table, |
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}; |
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static int __init davinci_psc_driver_init(void) |
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{ |
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return platform_driver_register(&davinci_psc_driver); |
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} |
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/* has to be postcore_initcall because davinci_gpio depend on PSC clocks */ |
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postcore_initcall(davinci_psc_driver_init);
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