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387 lines
9.9 KiB
387 lines
9.9 KiB
// SPDX-License-Identifier: GPL-2.0 |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/err.h> |
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#include <linux/errno.h> |
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#include <linux/gpio/consumer.h> |
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#include <linux/i2c.h> |
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#include <linux/regulator/consumer.h> |
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#include <dt-bindings/clock/maxim,max9485.h> |
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#define MAX9485_NUM_CLKS 4 |
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/* This chip has only one register of 8 bit width. */ |
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#define MAX9485_FS_12KHZ (0 << 0) |
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#define MAX9485_FS_32KHZ (1 << 0) |
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#define MAX9485_FS_44_1KHZ (2 << 0) |
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#define MAX9485_FS_48KHZ (3 << 0) |
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#define MAX9485_SCALE_256 (0 << 2) |
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#define MAX9485_SCALE_384 (1 << 2) |
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#define MAX9485_SCALE_768 (2 << 2) |
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#define MAX9485_DOUBLE BIT(4) |
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#define MAX9485_CLKOUT1_ENABLE BIT(5) |
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#define MAX9485_CLKOUT2_ENABLE BIT(6) |
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#define MAX9485_MCLK_ENABLE BIT(7) |
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#define MAX9485_FREQ_MASK 0x1f |
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struct max9485_rate { |
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unsigned long out; |
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u8 reg_value; |
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}; |
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/* |
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* Ordered by frequency. For frequency the hardware can generate with |
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* multiple settings, the one with lowest jitter is listed first. |
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*/ |
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static const struct max9485_rate max9485_rates[] = { |
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{ 3072000, MAX9485_FS_12KHZ | MAX9485_SCALE_256 }, |
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{ 4608000, MAX9485_FS_12KHZ | MAX9485_SCALE_384 }, |
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{ 8192000, MAX9485_FS_32KHZ | MAX9485_SCALE_256 }, |
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{ 9126000, MAX9485_FS_12KHZ | MAX9485_SCALE_768 }, |
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{ 11289600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 }, |
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{ 12288000, MAX9485_FS_48KHZ | MAX9485_SCALE_256 }, |
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{ 12288000, MAX9485_FS_32KHZ | MAX9485_SCALE_384 }, |
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{ 16384000, MAX9485_FS_32KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE }, |
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{ 16934400, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 }, |
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{ 18384000, MAX9485_FS_48KHZ | MAX9485_SCALE_384 }, |
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{ 22579200, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE }, |
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{ 24576000, MAX9485_FS_48KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE }, |
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{ 24576000, MAX9485_FS_32KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE }, |
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{ 24576000, MAX9485_FS_32KHZ | MAX9485_SCALE_768 }, |
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{ 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE }, |
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{ 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 }, |
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{ 36864000, MAX9485_FS_48KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE }, |
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{ 36864000, MAX9485_FS_48KHZ | MAX9485_SCALE_768 }, |
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{ 49152000, MAX9485_FS_32KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE }, |
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{ 67737600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE }, |
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{ 73728000, MAX9485_FS_48KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE }, |
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{ } /* sentinel */ |
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}; |
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struct max9485_driver_data; |
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struct max9485_clk_hw { |
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struct clk_hw hw; |
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struct clk_init_data init; |
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u8 enable_bit; |
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struct max9485_driver_data *drvdata; |
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}; |
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struct max9485_driver_data { |
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struct clk *xclk; |
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struct i2c_client *client; |
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u8 reg_value; |
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struct regulator *supply; |
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struct gpio_desc *reset_gpio; |
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struct max9485_clk_hw hw[MAX9485_NUM_CLKS]; |
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}; |
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static inline struct max9485_clk_hw *to_max9485_clk(struct clk_hw *hw) |
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{ |
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return container_of(hw, struct max9485_clk_hw, hw); |
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} |
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static int max9485_update_bits(struct max9485_driver_data *drvdata, |
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u8 mask, u8 value) |
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{ |
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int ret; |
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drvdata->reg_value &= ~mask; |
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drvdata->reg_value |= value; |
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dev_dbg(&drvdata->client->dev, |
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"updating mask 0x%02x value 0x%02x -> 0x%02x\n", |
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mask, value, drvdata->reg_value); |
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ret = i2c_master_send(drvdata->client, |
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&drvdata->reg_value, |
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sizeof(drvdata->reg_value)); |
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return ret < 0 ? ret : 0; |
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} |
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static int max9485_clk_prepare(struct clk_hw *hw) |
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{ |
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struct max9485_clk_hw *clk_hw = to_max9485_clk(hw); |
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return max9485_update_bits(clk_hw->drvdata, |
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clk_hw->enable_bit, |
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clk_hw->enable_bit); |
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} |
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static void max9485_clk_unprepare(struct clk_hw *hw) |
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{ |
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struct max9485_clk_hw *clk_hw = to_max9485_clk(hw); |
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max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0); |
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} |
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/* |
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* CLKOUT - configurable clock output |
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*/ |
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static int max9485_clkout_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct max9485_clk_hw *clk_hw = to_max9485_clk(hw); |
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const struct max9485_rate *entry; |
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for (entry = max9485_rates; entry->out != 0; entry++) |
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if (entry->out == rate) |
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break; |
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if (entry->out == 0) |
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return -EINVAL; |
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return max9485_update_bits(clk_hw->drvdata, |
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MAX9485_FREQ_MASK, |
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entry->reg_value); |
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} |
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static unsigned long max9485_clkout_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct max9485_clk_hw *clk_hw = to_max9485_clk(hw); |
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struct max9485_driver_data *drvdata = clk_hw->drvdata; |
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u8 val = drvdata->reg_value & MAX9485_FREQ_MASK; |
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const struct max9485_rate *entry; |
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for (entry = max9485_rates; entry->out != 0; entry++) |
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if (val == entry->reg_value) |
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return entry->out; |
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return 0; |
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} |
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static long max9485_clkout_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *parent_rate) |
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{ |
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const struct max9485_rate *curr, *prev = NULL; |
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for (curr = max9485_rates; curr->out != 0; curr++) { |
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/* Exact matches */ |
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if (curr->out == rate) |
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return rate; |
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/* |
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* Find the first entry that has a frequency higher than the |
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* requested one. |
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*/ |
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if (curr->out > rate) { |
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unsigned int mid; |
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/* |
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* If this is the first entry, clamp the value to the |
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* lowest possible frequency. |
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*/ |
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if (!prev) |
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return curr->out; |
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/* |
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* Otherwise, determine whether the previous entry or |
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* current one is closer. |
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*/ |
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mid = prev->out + ((curr->out - prev->out) / 2); |
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return (mid > rate) ? prev->out : curr->out; |
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} |
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prev = curr; |
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} |
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/* If the last entry was still too high, clamp the value */ |
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return prev->out; |
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} |
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struct max9485_clk { |
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const char *name; |
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int parent_index; |
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const struct clk_ops ops; |
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u8 enable_bit; |
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}; |
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static const struct max9485_clk max9485_clks[MAX9485_NUM_CLKS] = { |
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[MAX9485_MCLKOUT] = { |
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.name = "mclkout", |
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.parent_index = -1, |
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.enable_bit = MAX9485_MCLK_ENABLE, |
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.ops = { |
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.prepare = max9485_clk_prepare, |
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.unprepare = max9485_clk_unprepare, |
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}, |
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}, |
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[MAX9485_CLKOUT] = { |
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.name = "clkout", |
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.parent_index = -1, |
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.ops = { |
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.set_rate = max9485_clkout_set_rate, |
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.round_rate = max9485_clkout_round_rate, |
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.recalc_rate = max9485_clkout_recalc_rate, |
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}, |
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}, |
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[MAX9485_CLKOUT1] = { |
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.name = "clkout1", |
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.parent_index = MAX9485_CLKOUT, |
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.enable_bit = MAX9485_CLKOUT1_ENABLE, |
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.ops = { |
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.prepare = max9485_clk_prepare, |
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.unprepare = max9485_clk_unprepare, |
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}, |
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}, |
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[MAX9485_CLKOUT2] = { |
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.name = "clkout2", |
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.parent_index = MAX9485_CLKOUT, |
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.enable_bit = MAX9485_CLKOUT2_ENABLE, |
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.ops = { |
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.prepare = max9485_clk_prepare, |
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.unprepare = max9485_clk_unprepare, |
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}, |
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}, |
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}; |
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static struct clk_hw * |
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max9485_of_clk_get(struct of_phandle_args *clkspec, void *data) |
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{ |
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struct max9485_driver_data *drvdata = data; |
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unsigned int idx = clkspec->args[0]; |
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return &drvdata->hw[idx].hw; |
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} |
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static int max9485_i2c_probe(struct i2c_client *client, |
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const struct i2c_device_id *id) |
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{ |
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struct max9485_driver_data *drvdata; |
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struct device *dev = &client->dev; |
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const char *xclk_name; |
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int i, ret; |
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drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); |
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if (!drvdata) |
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return -ENOMEM; |
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drvdata->xclk = devm_clk_get(dev, "xclk"); |
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if (IS_ERR(drvdata->xclk)) |
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return PTR_ERR(drvdata->xclk); |
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xclk_name = __clk_get_name(drvdata->xclk); |
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drvdata->supply = devm_regulator_get(dev, "vdd"); |
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if (IS_ERR(drvdata->supply)) |
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return PTR_ERR(drvdata->supply); |
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ret = regulator_enable(drvdata->supply); |
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if (ret < 0) |
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return ret; |
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drvdata->reset_gpio = |
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devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); |
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if (IS_ERR(drvdata->reset_gpio)) |
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return PTR_ERR(drvdata->reset_gpio); |
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i2c_set_clientdata(client, drvdata); |
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drvdata->client = client; |
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ret = i2c_master_recv(drvdata->client, &drvdata->reg_value, |
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sizeof(drvdata->reg_value)); |
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if (ret < 0) { |
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dev_warn(dev, "Unable to read device register: %d\n", ret); |
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return ret; |
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} |
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for (i = 0; i < MAX9485_NUM_CLKS; i++) { |
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int parent_index = max9485_clks[i].parent_index; |
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const char *name; |
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if (of_property_read_string_index(dev->of_node, |
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"clock-output-names", |
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i, &name) == 0) { |
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drvdata->hw[i].init.name = name; |
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} else { |
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drvdata->hw[i].init.name = max9485_clks[i].name; |
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} |
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drvdata->hw[i].init.ops = &max9485_clks[i].ops; |
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drvdata->hw[i].init.num_parents = 1; |
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drvdata->hw[i].init.flags = 0; |
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if (parent_index > 0) { |
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drvdata->hw[i].init.parent_names = |
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&drvdata->hw[parent_index].init.name; |
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drvdata->hw[i].init.flags |= CLK_SET_RATE_PARENT; |
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} else { |
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drvdata->hw[i].init.parent_names = &xclk_name; |
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} |
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drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit; |
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drvdata->hw[i].hw.init = &drvdata->hw[i].init; |
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drvdata->hw[i].drvdata = drvdata; |
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ret = devm_clk_hw_register(dev, &drvdata->hw[i].hw); |
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if (ret < 0) |
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return ret; |
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} |
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return devm_of_clk_add_hw_provider(dev, max9485_of_clk_get, drvdata); |
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} |
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static int __maybe_unused max9485_suspend(struct device *dev) |
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{ |
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struct i2c_client *client = to_i2c_client(dev); |
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struct max9485_driver_data *drvdata = i2c_get_clientdata(client); |
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gpiod_set_value_cansleep(drvdata->reset_gpio, 0); |
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return 0; |
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} |
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static int __maybe_unused max9485_resume(struct device *dev) |
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{ |
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struct i2c_client *client = to_i2c_client(dev); |
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struct max9485_driver_data *drvdata = i2c_get_clientdata(client); |
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int ret; |
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gpiod_set_value_cansleep(drvdata->reset_gpio, 1); |
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ret = i2c_master_send(client, &drvdata->reg_value, |
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sizeof(drvdata->reg_value)); |
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return ret < 0 ? ret : 0; |
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} |
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static const struct dev_pm_ops max9485_pm_ops = { |
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SET_SYSTEM_SLEEP_PM_OPS(max9485_suspend, max9485_resume) |
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}; |
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static const struct of_device_id max9485_dt_ids[] = { |
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{ .compatible = "maxim,max9485", }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, max9485_dt_ids); |
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static const struct i2c_device_id max9485_i2c_ids[] = { |
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{ .name = "max9485", }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(i2c, max9485_i2c_ids); |
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static struct i2c_driver max9485_driver = { |
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.driver = { |
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.name = "max9485", |
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.pm = &max9485_pm_ops, |
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.of_match_table = max9485_dt_ids, |
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}, |
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.probe = max9485_i2c_probe, |
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.id_table = max9485_i2c_ids, |
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}; |
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module_i2c_driver(max9485_driver); |
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MODULE_AUTHOR("Daniel Mack <[email protected]>"); |
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MODULE_DESCRIPTION("MAX9485 Programmable Audio Clock Generator"); |
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MODULE_LICENSE("GPL v2");
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